sramtest.tan.qmsg

FPGA的SRAM存储器的控制程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLOCK_50 register Reset_Delay:r0\|Cont\[18\] register Reset_Delay:r0\|Cont\[18\] 293.77 MHz 3.404 ns Internal " "Info: Clock \"CLOCK_50\" has Internal fmax of 293.77 MHz between source register \"Reset_Delay:r0\|Cont\[18\]\" and destination register \"Reset_Delay:r0\|Cont\[18\]\" (period= 3.404 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.190 ns + Longest register register " "Info: + Longest register to register delay is 3.190 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Reset_Delay:r0\|Cont\[18\] 1 REG LCFF_X14_Y1_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y1_N17; Fanout = 3; REG Node = 'Reset_Delay:r0\|Cont\[18\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(0.410 ns) 0.735 ns Reset_Delay:r0\|Equal0~196 2 COMB LCCOMB_X14_Y1_N20 1 " "Info: 2: + IC(0.325 ns) + CELL(0.410 ns) = 0.735 ns; Loc. = LCCOMB_X14_Y1_N20; Fanout = 1; COMB Node = 'Reset_Delay:r0\|Equal0~196'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { Reset_Delay:r0|Cont[18] Reset_Delay:r0|Equal0~196 } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.690 ns) + CELL(0.438 ns) 1.863 ns Reset_Delay:r0\|Equal0~197 3 COMB LCCOMB_X14_Y2_N10 21 " "Info: 3: + IC(0.690 ns) + CELL(0.438 ns) = 1.863 ns; Loc. = LCCOMB_X14_Y2_N10; Fanout = 21; COMB Node = 'Reset_Delay:r0\|Equal0~197'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.128 ns" { Reset_Delay:r0|Equal0~196 Reset_Delay:r0|Equal0~197 } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.660 ns) 3.190 ns Reset_Delay:r0\|Cont\[18\] 4 REG LCFF_X14_Y1_N17 3 " "Info: 4: + IC(0.667 ns) + CELL(0.660 ns) = 3.190 ns; Loc. = LCFF_X14_Y1_N17; Fanout = 3; REG Node = 'Reset_Delay:r0\|Cont\[18\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.327 ns" { Reset_Delay:r0|Equal0~197 Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.508 ns ( 47.27 % ) " "Info: Total cell delay = 1.508 ns ( 47.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.682 ns ( 52.73 % ) " "Info: Total interconnect delay = 1.682 ns ( 52.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { Reset_Delay:r0|Cont[18] Reset_Delay:r0|Equal0~196 Reset_Delay:r0|Equal0~197 Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { Reset_Delay:r0|Cont[18] Reset_Delay:r0|Equal0~196 Reset_Delay:r0|Equal0~197 Reset_Delay:r0|Cont[18] } { 0.000ns 0.325ns 0.690ns 0.667ns } { 0.000ns 0.410ns 0.438ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.707 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.053 ns) + CELL(0.537 ns) 2.707 ns Reset_Delay:r0\|Cont\[18\] 3 REG LCFF_X14_Y1_N17 3 " "Info: 3: + IC(1.053 ns) + CELL(0.537 ns) = 2.707 ns; Loc. = LCFF_X14_Y1_N17; Fanout = 3; REG Node = 'Reset_Delay:r0\|Cont\[18\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.74 % ) " "Info: Total cell delay = 1.536 ns ( 56.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.171 ns ( 43.26 % ) " "Info: Total interconnect delay = 1.171 ns ( 43.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.707 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } { 0.000ns 0.000ns 0.118ns 1.053ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.707 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 2.707 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.053 ns) + CELL(0.537 ns) 2.707 ns Reset_Delay:r0\|Cont\[18\] 3 REG LCFF_X14_Y1_N17 3 " "Info: 3: + IC(1.053 ns) + CELL(0.537 ns) = 2.707 ns; Loc. = LCFF_X14_Y1_N17; Fanout = 3; REG Node = 'Reset_Delay:r0\|Cont\[18\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.590 ns" { CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.74 % ) " "Info: Total cell delay = 1.536 ns ( 56.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.171 ns ( 43.26 % ) " "Info: Total interconnect delay = 1.171 ns ( 43.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.707 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } { 0.000ns 0.000ns 0.118ns 1.053ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.707 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } { 0.000ns 0.000ns 0.118ns 1.053ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.707 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } { 0.000ns 0.000ns 0.118ns 1.053ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 6 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 6 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.190 ns" { Reset_Delay:r0|Cont[18] Reset_Delay:r0|Equal0~196 Reset_Delay:r0|Equal0~197 Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.190 ns" { Reset_Delay:r0|Cont[18] Reset_Delay:r0|Equal0~196 Reset_Delay:r0|Equal0~197 Reset_Delay:r0|Cont[18] } { 0.000ns 0.325ns 0.690ns 0.667ns } { 0.000ns 0.410ns 0.438ns 0.660ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.707 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } { 0.000ns 0.000ns 0.118ns 1.053ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.707 ns" { CLOCK_50 CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.707 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl Reset_Delay:r0|Cont[18] } { 0.000ns 0.000ns 0.118ns 1.053ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "temp_DATA\[0\] KEY\[0\] CLOCK_50 7.277 ns register " "Info: tsu for register \"temp_DATA\[0\]\" (data pin = \"KEY\[0\]\", clock pin = \"CLOCK_50\") is 7.277 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.015 ns + Longest pin register " "Info: + Longest pin to register delay is 10.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns KEY\[0\] 1 PIN PIN_G26 6 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 6; PIN Node = 'KEY\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { KEY[0] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.189 ns) + CELL(0.413 ns) 8.464 ns temp_DATA\[0\]~136 2 COMB LCCOMB_X15_Y1_N18 16 " "Info: 2: + IC(7.189 ns) + CELL(0.413 ns) = 8.464 ns; Loc. = LCCOMB_X15_Y1_N18; Fanout = 16; COMB Node = 'temp_DATA\[0\]~136'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.602 ns" { KEY[0] temp_DATA[0]~136 } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.891 ns) + CELL(0.660 ns) 10.015 ns temp_DATA\[0\] 3 REG LCFF_X22_Y1_N21 1 " "Info: 3: + IC(0.891 ns) + CELL(0.660 ns) = 10.015 ns; Loc. = LCFF_X22_Y1_N21; Fanout = 1; REG Node = 'temp_DATA\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.551 ns" { temp_DATA[0]~136 temp_DATA[0] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.935 ns ( 19.32 % ) " "Info: Total cell delay = 1.935 ns ( 19.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.080 ns ( 80.68 % ) " "Info: Total interconnect delay = 8.080 ns ( 80.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.015 ns" { KEY[0] temp_DATA[0]~136 temp_DATA[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.015 ns" { KEY[0] KEY[0]~combout temp_DATA[0]~136 temp_DATA[0] } { 0.000ns 0.000ns 7.189ns 0.891ns } { 0.000ns 0.862ns 0.413ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 100 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.702 ns - Shortest register " "Info: - Shortest clock path from clock \"CLOCK_50\" to destination register is 2.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.537 ns) 2.702 ns temp_DATA\[0\] 3 REG LCFF_X22_Y1_N21 1 " "Info: 3: + IC(1.048 ns) + CELL(0.537 ns) = 2.702 ns; Loc. = LCFF_X22_Y1_N21; Fanout = 1; REG Node = 'temp_DATA\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { CLOCK_50~clkctrl temp_DATA[0] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.85 % ) " "Info: Total cell delay = 1.536 ns ( 56.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.166 ns ( 43.15 % ) " "Info: Total interconnect delay = 1.166 ns ( 43.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.702 ns" { CLOCK_50 CLOCK_50~clkctrl temp_DATA[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.702 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl temp_DATA[0] } { 0.000ns 0.000ns 0.118ns 1.048ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "10.015 ns" { KEY[0] temp_DATA[0]~136 temp_DATA[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "10.015 ns" { KEY[0] KEY[0]~combout temp_DATA[0]~136 temp_DATA[0] } { 0.000ns 0.000ns 7.189ns 0.891ns } { 0.000ns 0.862ns 0.413ns 0.660ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.702 ns" { CLOCK_50 CLOCK_50~clkctrl temp_DATA[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.702 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl temp_DATA[0] } { 0.000ns 0.000ns 0.118ns 1.048ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLOCK_50 HEX1\[3\] SEG7_LUT_4:seg_4\|temp_DIG\[4\] 10.450 ns register " "Info: tco from clock \"CLOCK_50\" to destination pin \"HEX1\[3\]\" through register \"SEG7_LUT_4:seg_4\|temp_DIG\[4\]\" is 10.450 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 2.702 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to source register is 2.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.048 ns) + CELL(0.537 ns) 2.702 ns SEG7_LUT_4:seg_4\|temp_DIG\[4\] 3 REG LCFF_X22_Y1_N11 7 " "Info: 3: + IC(1.048 ns) + CELL(0.537 ns) = 2.702 ns; Loc. = LCFF_X22_Y1_N11; Fanout = 7; REG Node = 'SEG7_LUT_4:seg_4\|temp_DIG\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.585 ns" { CLOCK_50~clkctrl SEG7_LUT_4:seg_4|temp_DIG[4] } "NODE_NAME" } } { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.85 % ) " "Info: Total cell delay = 1.536 ns ( 56.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.166 ns ( 43.15 % ) " "Info: Total interconnect delay = 1.166 ns ( 43.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.702 ns" { CLOCK_50 CLOCK_50~clkctrl SEG7_LUT_4:seg_4|temp_DIG[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.702 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl SEG7_LUT_4:seg_4|temp_DIG[4] } { 0.000ns 0.000ns 0.118ns 1.048ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.498 ns + Longest register pin " "Info: + Longest register to pin delay is 7.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SEG7_LUT_4:seg_4\|temp_DIG\[4\] 1 REG LCFF_X22_Y1_N11 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y1_N11; Fanout = 7; REG Node = 'SEG7_LUT_4:seg_4\|temp_DIG\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SEG7_LUT_4:seg_4|temp_DIG[4] } "NODE_NAME" } } { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.438 ns) 0.975 ns SEG7_LUT_4:seg_4\|SEG7_LUT:u1\|WideOr3~19 2 COMB LCCOMB_X23_Y1_N30 1 " "Info: 2: + IC(0.537 ns) + CELL(0.438 ns) = 0.975 ns; Loc. = LCCOMB_X23_Y1_N30; Fanout = 1; COMB Node = 'SEG7_LUT_4:seg_4\|SEG7_LUT:u1\|WideOr3~19'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { SEG7_LUT_4:seg_4|temp_DIG[4] SEG7_LUT_4:seg_4|SEG7_LUT:u1|WideOr3~19 } "NODE_NAME" } } { "SEG7_LUT.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.901 ns) + CELL(2.622 ns) 7.498 ns HEX1\[3\] 3 PIN PIN_Y22 0 " "Info: 3: + IC(3.901 ns) + CELL(2.622 ns) = 7.498 ns; Loc. = PIN_Y22; Fanout = 0; PIN Node = 'HEX1\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.523 ns" { SEG7_LUT_4:seg_4|SEG7_LUT:u1|WideOr3~19 HEX1[3] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.060 ns ( 40.81 % ) " "Info: Total cell delay = 3.060 ns ( 40.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.438 ns ( 59.19 % ) " "Info: Total interconnect delay = 4.438 ns ( 59.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.498 ns" { SEG7_LUT_4:seg_4|temp_DIG[4] SEG7_LUT_4:seg_4|SEG7_LUT:u1|WideOr3~19 HEX1[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.498 ns" { SEG7_LUT_4:seg_4|temp_DIG[4] SEG7_LUT_4:seg_4|SEG7_LUT:u1|WideOr3~19 HEX1[3] } { 0.000ns 0.537ns 3.901ns } { 0.000ns 0.438ns 2.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.702 ns" { CLOCK_50 CLOCK_50~clkctrl SEG7_LUT_4:seg_4|temp_DIG[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.702 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl SEG7_LUT_4:seg_4|temp_DIG[4] } { 0.000ns 0.000ns 0.118ns 1.048ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.498 ns" { SEG7_LUT_4:seg_4|temp_DIG[4] SEG7_LUT_4:seg_4|SEG7_LUT:u1|WideOr3~19 HEX1[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.498 ns" { SEG7_LUT_4:seg_4|temp_DIG[4] SEG7_LUT_4:seg_4|SEG7_LUT:u1|WideOr3~19 HEX1[3] } { 0.000ns 0.537ns 3.901ns } { 0.000ns 0.438ns 2.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[16\] LEDR\[16\] 9.902 ns Longest " "Info: Longest tpd from source pin \"SW\[16\]\" to destination pin \"LEDR\[16\]\" is 9.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns SW\[16\] 1 PIN PIN_V1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V1; Fanout = 2; PIN Node = 'SW\[16\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[16] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.252 ns) + CELL(2.798 ns) 9.902 ns LEDR\[16\] 2 PIN PIN_AE12 0 " "Info: 2: + IC(6.252 ns) + CELL(2.798 ns) = 9.902 ns; Loc. = PIN_AE12; Fanout = 0; PIN Node = 'LEDR\[16\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.050 ns" { SW[16] LEDR[16] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.650 ns ( 36.86 % ) " "Info: Total cell delay = 3.650 ns ( 36.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.252 ns ( 63.14 % ) " "Info: Total interconnect delay = 6.252 ns ( 63.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "9.902 ns" { SW[16] LEDR[16] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "9.902 ns" { SW[16] SW[16]~combout LEDR[16] } { 0.000ns 0.000ns 6.252ns } { 0.000ns 0.852ns 2.798ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}