📄 waveform1.vwf

📁 FPGA的SRAM存储器的控制程序
💻 VWF
📖 第 1 页 / 共 4 页
字号:
上一页 1 2 34
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 32;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 33;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 34;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 35;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 36;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_LB_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 37;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_OE_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 38;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_UB_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 39;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_WE_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 40;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 41;
	TREE_LEVEL = 0;
	CHILDREN = 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[17]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 42;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[16]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 43;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 44;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 45;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 46;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 47;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 48;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 49;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 50;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 51;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 52;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 53;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 54;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 55;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 56;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 57;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 58;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 59;
	TREE_LEVEL = 1;
	PARENT = 41;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 60;
	TREE_LEVEL = 0;
	CHILDREN = 61, 62;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 61;
	TREE_LEVEL = 1;
	PARENT = 60;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 62;
	TREE_LEVEL = 1;
	PARENT = 60;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iCE_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 63;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iCLK";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 64;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 65;
	TREE_LEVEL = 0;
	CHILDREN = 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 66;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 67;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 68;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 69;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 70;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 71;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 72;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 73;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 74;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 75;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 76;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 77;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 78;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 79;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 80;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 81;
	TREE_LEVEL = 1;
	PARENT = 65;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iOE_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 82;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iWE_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 83;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 84;
	TREE_LEVEL = 0;
	CHILDREN = 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 85;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 86;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 87;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 88;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 89;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 90;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 91;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 92;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 93;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 94;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 95;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 96;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 97;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 98;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 99;
	TREE_LEVEL = 1;
	PARENT = 84;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 100;
	TREE_LEVEL = 1;
	PARENT = 84;
}

TIME_BAR
{
	TIME = 11950;
	MASTER = TRUE;
}
;
上一页 1 2 34
💿 文件大小 652 K
👤 上传用户 qingriwanxia
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FPGA #SRAM #存储器 #控制
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -