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📄 waveform1.vwf

📁 FPGA的SRAM存储器的控制程序
💻 VWF
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1234 
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iCE_N")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iCLK")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL U FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iOE_N")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iWE_N")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 1000.0;
	}
}

TRANSITION_LIST("SRAM_16Bit_512K:the_SRAM_16Bit_512K|oDATA[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
	CHILDREN = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[17]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 1;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[16]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 6;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 7;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[8]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 13;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 14;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_CE_N";
	EXPAND_STATUS = COLLAPSED;
	RADIX = ASCII;
	TREE_INDEX = 19;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 20;
	TREE_LEVEL = 0;
	CHILDREN = 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[15]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[14]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[13]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 23;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[12]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 24;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[11]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[10]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[9]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 20;
}

DISPLAY_LINE
{
	CHANNEL = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[8]";
1234

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