_primary.vhd

来自「FPGA的SRAM存储器的控制程序」· VHDL 代码 · 共 23 行

library verilog;
use verilog.vl_types.all;
entity SRAMtest is
    port(
        CLOCK_50        : in     vl_logic;
        SW              : in     vl_logic_vector(11 downto 0);
        LEDR            : out    vl_logic_vector(17 downto 0);
        D_A             : in     vl_logic;
        W_R             : in     vl_logic;
        HEX0            : out    vl_logic_vector(6 downto 0);
        HEX1            : out    vl_logic_vector(6 downto 0);
        HEX2            : out    vl_logic_vector(6 downto 0);
        HEX3            : out    vl_logic_vector(6 downto 0);
        SRAM_ADDR       : out    vl_logic_vector(17 downto 0);
        SRAM_UB_N       : out    vl_logic;
        SRAM_LB_N       : out    vl_logic;
        SRAM_WE_N       : out    vl_logic;
        SRAM_CE_N       : out    vl_logic;
        SRAM_OE_N       : out    vl_logic;
        SRAM_DQ         : inout  vl_logic_vector(15 downto 0)
    );
end SRAMtest;