config_dac.fit.summary

来自「Verilog实现 spi接口的FPGA实现 通过仿真」· SUMMARY 代码 · 共 17 行

Fitter Status : Successful - Tue Aug 19 14:15:35 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : config_dac
Top-level Entity Name : config_dac
Family : Cyclone II
Device : EP2C5T144C6
Timing Models : Final
Total logic elements : 70 / 4,608 ( 2 % )
    Total combinational functions : 39 / 4,608 ( < 1 % )
    Dedicated logic registers : 59 / 4,608 ( 1 % )
Total registers : 59
Total pins : 31 / 89 ( 35 % )
Total virtual pins : 0
Total memory bits : 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )