_primary.vhd

来自「Verilog实现 spi接口的FPGA实现 通过仿真」· VHDL 代码 · 共 27 行

library verilog;
use verilog.vl_types.all;
entity config_dac is
    generic(
        IDLE            : integer := 1;
        START           : integer := 2;
        INSTRUCTION     : integer := 4;
        DATA            : integer := 8;
        STOP            : integer := 16
    );
    port(
        clk             : in     vl_logic;
        resetb          : in     vl_logic;
        wr_rd_addr      : in     vl_logic_vector(4 downto 0);
        wr_en           : in     vl_logic;
        wr_data         : in     vl_logic_vector(7 downto 0);
        rd_en           : in     vl_logic;
        rd_data         : out    vl_logic_vector(7 downto 0);
        rd_data_valid   : out    vl_logic;
        busy            : out    vl_logic;
        spi_ncs         : out    vl_logic;
        spi_sdio        : out    vl_logic;
        spi_sdo         : in     vl_logic;
        spi_sck         : out    vl_logic
    );
end config_dac;