config_dac.smp_dump.txt

Verilog实现 spi接口的FPGA实现 通过仿真

State Machine - |config_dac|main_state
Name main_state.STOP main_state.DATA main_state.INSTRUCTION main_state.START main_state.IDLE 
main_state.IDLE 0 0 0 0 0 
main_state.DATA 0 1 0 0 1 
main_state.INSTRUCTION 0 0 1 0 1 
main_state.START 0 0 0 1 1 
main_state.STOP 1 0 0 0 1