config_dac.tan.qmsg

Verilog实现 spi接口的FPGA实现 通过仿真

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sck_count\[0\] register data_to_send\[7\] 357.78 MHz 2.795 ns Internal " "Info: Clock \"clk\" has Internal fmax of 357.78 MHz between source register \"sck_count\[0\]\" and destination register \"data_to_send\[7\]\" (period= 2.795 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.582 ns + Longest register register " "Info: + Longest register to register delay is 2.582 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sck_count\[0\] 1 REG LCFF_X21_Y6_N27 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y6_N27; Fanout = 11; REG Node = 'sck_count\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sck_count[0] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(0.437 ns) 1.690 ns data_to_send\[7\]~905 2 COMB LCCOMB_X22_Y6_N8 7 " "Info: 2: + IC(1.253 ns) + CELL(0.437 ns) = 1.690 ns; Loc. = LCCOMB_X22_Y6_N8; Fanout = 7; COMB Node = 'data_to_send\[7\]~905'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.690 ns" { sck_count[0] data_to_send[7]~905 } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.232 ns) + CELL(0.660 ns) 2.582 ns data_to_send\[7\] 3 REG LCFF_X22_Y6_N13 1 " "Info: 3: + IC(0.232 ns) + CELL(0.660 ns) = 2.582 ns; Loc. = LCFF_X22_Y6_N13; Fanout = 1; REG Node = 'data_to_send\[7\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.892 ns" { data_to_send[7]~905 data_to_send[7] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.097 ns ( 42.49 % ) " "Info: Total cell delay = 1.097 ns ( 42.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.485 ns ( 57.51 % ) " "Info: Total interconnect delay = 1.485 ns ( 57.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.582 ns" { sck_count[0] data_to_send[7]~905 data_to_send[7] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.582 ns" { sck_count[0] data_to_send[7]~905 data_to_send[7] } { 0.000ns 1.253ns 0.232ns } { 0.000ns 0.437ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.343 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.343 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 59 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 59; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.695 ns) + CELL(0.537 ns) 2.343 ns data_to_send\[7\] 3 REG LCFF_X22_Y6_N13 1 " "Info: 3: + IC(0.695 ns) + CELL(0.537 ns) = 2.343 ns; Loc. = LCFF_X22_Y6_N13; Fanout = 1; REG Node = 'data_to_send\[7\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.232 ns" { clk~clkctrl data_to_send[7] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.13 % ) " "Info: Total cell delay = 1.526 ns ( 65.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.817 ns ( 34.87 % ) " "Info: Total interconnect delay = 0.817 ns ( 34.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.343 ns" { clk clk~clkctrl data_to_send[7] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.343 ns" { clk clk~combout clk~clkctrl data_to_send[7] } { 0.000ns 0.000ns 0.122ns 0.695ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.342 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.342 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 59 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 59; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.694 ns) + CELL(0.537 ns) 2.342 ns sck_count\[0\] 3 REG LCFF_X21_Y6_N27 11 " "Info: 3: + IC(0.694 ns) + CELL(0.537 ns) = 2.342 ns; Loc. = LCFF_X21_Y6_N27; Fanout = 11; REG Node = 'sck_count\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.231 ns" { clk~clkctrl sck_count[0] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 118 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.16 % ) " "Info: Total cell delay = 1.526 ns ( 65.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.816 ns ( 34.84 % ) " "Info: Total interconnect delay = 0.816 ns ( 34.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.342 ns" { clk clk~clkctrl sck_count[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.342 ns" { clk clk~combout clk~clkctrl sck_count[0] } { 0.000ns 0.000ns 0.122ns 0.694ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.343 ns" { clk clk~clkctrl data_to_send[7] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.343 ns" { clk clk~combout clk~clkctrl data_to_send[7] } { 0.000ns 0.000ns 0.122ns 0.695ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.342 ns" { clk clk~clkctrl sck_count[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.342 ns" { clk clk~combout clk~clkctrl sck_count[0] } { 0.000ns 0.000ns 0.122ns 0.694ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 118 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 141 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.582 ns" { sck_count[0] data_to_send[7]~905 data_to_send[7] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.582 ns" { sck_count[0] data_to_send[7]~905 data_to_send[7] } { 0.000ns 1.253ns 0.232ns } { 0.000ns 0.437ns 0.660ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.343 ns" { clk clk~clkctrl data_to_send[7] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.343 ns" { clk clk~combout clk~clkctrl data_to_send[7] } { 0.000ns 0.000ns 0.122ns 0.695ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.342 ns" { clk clk~clkctrl sck_count[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.342 ns" { clk clk~combout clk~clkctrl sck_count[0] } { 0.000ns 0.000ns 0.122ns 0.694ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "waddr\[4\] wr_en clk 5.482 ns register " "Info: tsu for register \"waddr\[4\]\" (data pin = \"wr_en\", clock pin = \"clk\") is 5.482 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.866 ns + Longest pin register " "Info: + Longest pin to register delay is 7.866 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns wr_en 1 PIN PIN_79 10 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_79; Fanout = 10; PIN Node = 'wr_en'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_en } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.263 ns) + CELL(0.420 ns) 6.535 ns always1~0 2 COMB LCCOMB_X20_Y6_N2 7 " "Info: 2: + IC(5.263 ns) + CELL(0.420 ns) = 6.535 ns; Loc. = LCCOMB_X20_Y6_N2; Fanout = 7; COMB Node = 'always1~0'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.683 ns" { wr_en always1~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.660 ns) 7.866 ns waddr\[4\] 3 REG LCFF_X24_Y6_N5 1 " "Info: 3: + IC(0.671 ns) + CELL(0.660 ns) = 7.866 ns; Loc. = LCFF_X24_Y6_N5; Fanout = 1; REG Node = 'waddr\[4\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.331 ns" { always1~0 waddr[4] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.932 ns ( 24.56 % ) " "Info: Total cell delay = 1.932 ns ( 24.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.934 ns ( 75.44 % ) " "Info: Total interconnect delay = 5.934 ns ( 75.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.866 ns" { wr_en always1~0 waddr[4] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.866 ns" { wr_en wr_en~combout always1~0 waddr[4] } { 0.000ns 0.000ns 5.263ns 0.671ns } { 0.000ns 0.852ns 0.420ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 65 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 59 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 59; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.537 ns) 2.348 ns waddr\[4\] 3 REG LCFF_X24_Y6_N5 1 " "Info: 3: + IC(0.700 ns) + CELL(0.537 ns) = 2.348 ns; Loc. = LCFF_X24_Y6_N5; Fanout = 1; REG Node = 'waddr\[4\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.237 ns" { clk~clkctrl waddr[4] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.99 % ) " "Info: Total cell delay = 1.526 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.822 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.822 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk clk~clkctrl waddr[4] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk clk~combout clk~clkctrl waddr[4] } { 0.000ns 0.000ns 0.122ns 0.700ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.866 ns" { wr_en always1~0 waddr[4] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.866 ns" { wr_en wr_en~combout always1~0 waddr[4] } { 0.000ns 0.000ns 5.263ns 0.671ns } { 0.000ns 0.852ns 0.420ns 0.660ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk clk~clkctrl waddr[4] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk clk~combout clk~clkctrl waddr[4] } { 0.000ns 0.000ns 0.122ns 0.700ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk rd_data\[3\] rd_data\[3\]~reg0 7.073 ns register " "Info: tco from clock \"clk\" to destination pin \"rd_data\[3\]\" through register \"rd_data\[3\]~reg0\" is 7.073 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.342 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.342 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 59 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 59; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.694 ns) + CELL(0.537 ns) 2.342 ns rd_data\[3\]~reg0 3 REG LCFF_X21_Y6_N9 1 " "Info: 3: + IC(0.694 ns) + CELL(0.537 ns) = 2.342 ns; Loc. = LCFF_X21_Y6_N9; Fanout = 1; REG Node = 'rd_data\[3\]~reg0'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.231 ns" { clk~clkctrl rd_data[3]~reg0 } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 175 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.16 % ) " "Info: Total cell delay = 1.526 ns ( 65.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.816 ns ( 34.84 % ) " "Info: Total interconnect delay = 0.816 ns ( 34.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.342 ns" { clk clk~clkctrl rd_data[3]~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.342 ns" { clk clk~combout clk~clkctrl rd_data[3]~reg0 } { 0.000ns 0.000ns 0.122ns 0.694ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 175 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.481 ns + Longest register pin " "Info: + Longest register to pin delay is 4.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rd_data\[3\]~reg0 1 REG LCFF_X21_Y6_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y6_N9; Fanout = 1; REG Node = 'rd_data\[3\]~reg0'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { rd_data[3]~reg0 } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 175 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.693 ns) + CELL(2.788 ns) 4.481 ns rd_data\[3\] 2 PIN PIN_129 0 " "Info: 2: + IC(1.693 ns) + CELL(2.788 ns) = 4.481 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'rd_data\[3\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.481 ns" { rd_data[3]~reg0 rd_data[3] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 175 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.788 ns ( 62.22 % ) " "Info: Total cell delay = 2.788 ns ( 62.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.693 ns ( 37.78 % ) " "Info: Total interconnect delay = 1.693 ns ( 37.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.481 ns" { rd_data[3]~reg0 rd_data[3] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.481 ns" { rd_data[3]~reg0 rd_data[3] } { 0.000ns 1.693ns } { 0.000ns 2.788ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.342 ns" { clk clk~clkctrl rd_data[3]~reg0 } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.342 ns" { clk clk~combout clk~clkctrl rd_data[3]~reg0 } { 0.000ns 0.000ns 0.122ns 0.694ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.481 ns" { rd_data[3]~reg0 rd_data[3] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.481 ns" { rd_data[3]~reg0 rd_data[3] } { 0.000ns 1.693ns } { 0.000ns 2.788ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "waddr\[3\] wr_rd_addr\[3\] clk 0.522 ns register " "Info: th for register \"waddr\[3\]\" (data pin = \"wr_rd_addr\[3\]\", clock pin = \"clk\") is 0.522 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 59 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 59; COMB Node = 'clk~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.537 ns) 2.348 ns waddr\[3\] 3 REG LCFF_X24_Y6_N29 1 " "Info: 3: + IC(0.700 ns) + CELL(0.537 ns) = 2.348 ns; Loc. = LCFF_X24_Y6_N29; Fanout = 1; REG Node = 'waddr\[3\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.237 ns" { clk~clkctrl waddr[3] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.99 % ) " "Info: Total cell delay = 1.526 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.822 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.822 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk clk~clkctrl waddr[3] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk clk~combout clk~clkctrl waddr[3] } { 0.000ns 0.000ns 0.122ns 0.700ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 65 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.092 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns wr_rd_addr\[3\] 1 PIN PIN_90 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_90; Fanout = 1; PIN Node = 'wr_rd_addr\[3\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_rd_addr[3] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.860 ns) + CELL(0.149 ns) 2.008 ns waddr\[3\]~feeder 2 COMB LCCOMB_X24_Y6_N28 1 " "Info: 2: + IC(0.860 ns) + CELL(0.149 ns) = 2.008 ns; Loc. = LCCOMB_X24_Y6_N28; Fanout = 1; COMB Node = 'waddr\[3\]~feeder'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { wr_rd_addr[3] waddr[3]~feeder } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.092 ns waddr\[3\] 3 REG LCFF_X24_Y6_N29 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.092 ns; Loc. = LCFF_X24_Y6_N29; Fanout = 1; REG Node = 'waddr\[3\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { waddr[3]~feeder waddr[3] } "NODE_NAME" } } { "config_dac.v" "" { Text "D:/altera/71/config_dac/config_dac.v" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.232 ns ( 58.89 % ) " "Info: Total cell delay = 1.232 ns ( 58.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.860 ns ( 41.11 % ) " "Info: Total interconnect delay = 0.860 ns ( 41.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.092 ns" { wr_rd_addr[3] waddr[3]~feeder waddr[3] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.092 ns" { wr_rd_addr[3] wr_rd_addr[3]~combout waddr[3]~feeder waddr[3] } { 0.000ns 0.000ns 0.860ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk clk~clkctrl waddr[3] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk clk~combout clk~clkctrl waddr[3] } { 0.000ns 0.000ns 0.122ns 0.700ns } { 0.000ns 0.989ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.092 ns" { wr_rd_addr[3] waddr[3]~feeder waddr[3] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.092 ns" { wr_rd_addr[3] wr_rd_addr[3]~combout waddr[3]~feeder waddr[3] } { 0.000ns 0.000ns 0.860ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}