config_dac.vo

Verilog实现 spi接口的FPGA实现 通过仿真

	.regout(),
	.differentialout(),
	.linkout(),
	.padio(wr_data[1]));
// synopsys translate_off
defparam \wr_data[1]~I .input_async_reset = "none";
defparam \wr_data[1]~I .input_power_up = "low";
defparam \wr_data[1]~I .input_register_mode = "none";
defparam \wr_data[1]~I .input_sync_reset = "none";
defparam \wr_data[1]~I .oe_async_reset = "none";
defparam \wr_data[1]~I .oe_power_up = "low";
defparam \wr_data[1]~I .oe_register_mode = "none";
defparam \wr_data[1]~I .oe_sync_reset = "none";
defparam \wr_data[1]~I .operation_mode = "input";
defparam \wr_data[1]~I .output_async_reset = "none";
defparam \wr_data[1]~I .output_power_up = "low";
defparam \wr_data[1]~I .output_register_mode = "none";
defparam \wr_data[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_93
cycloneii_io \wr_rd_addr[1]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\wr_rd_addr~combout [1]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(wr_rd_addr[1]));
// synopsys translate_off
defparam \wr_rd_addr[1]~I .input_async_reset = "none";
defparam \wr_rd_addr[1]~I .input_power_up = "low";
defparam \wr_rd_addr[1]~I .input_register_mode = "none";
defparam \wr_rd_addr[1]~I .input_sync_reset = "none";
defparam \wr_rd_addr[1]~I .oe_async_reset = "none";
defparam \wr_rd_addr[1]~I .oe_power_up = "low";
defparam \wr_rd_addr[1]~I .oe_register_mode = "none";
defparam \wr_rd_addr[1]~I .oe_sync_reset = "none";
defparam \wr_rd_addr[1]~I .operation_mode = "input";
defparam \wr_rd_addr[1]~I .output_async_reset = "none";
defparam \wr_rd_addr[1]~I .output_power_up = "low";
defparam \wr_rd_addr[1]~I .output_register_mode = "none";
defparam \wr_rd_addr[1]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_64
cycloneii_io \wr_data[0]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\wr_data~combout [0]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(wr_data[0]));
// synopsys translate_off
defparam \wr_data[0]~I .input_async_reset = "none";
defparam \wr_data[0]~I .input_power_up = "low";
defparam \wr_data[0]~I .input_register_mode = "none";
defparam \wr_data[0]~I .input_sync_reset = "none";
defparam \wr_data[0]~I .oe_async_reset = "none";
defparam \wr_data[0]~I .oe_power_up = "low";
defparam \wr_data[0]~I .oe_register_mode = "none";
defparam \wr_data[0]~I .oe_sync_reset = "none";
defparam \wr_data[0]~I .operation_mode = "input";
defparam \wr_data[0]~I .output_async_reset = "none";
defparam \wr_data[0]~I .output_power_up = "low";
defparam \wr_data[0]~I .output_register_mode = "none";
defparam \wr_data[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_63
cycloneii_io \wr_rd_addr[0]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\wr_rd_addr~combout [0]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(wr_rd_addr[0]));
// synopsys translate_off
defparam \wr_rd_addr[0]~I .input_async_reset = "none";
defparam \wr_rd_addr[0]~I .input_power_up = "low";
defparam \wr_rd_addr[0]~I .input_register_mode = "none";
defparam \wr_rd_addr[0]~I .input_sync_reset = "none";
defparam \wr_rd_addr[0]~I .oe_async_reset = "none";
defparam \wr_rd_addr[0]~I .oe_power_up = "low";
defparam \wr_rd_addr[0]~I .oe_register_mode = "none";
defparam \wr_rd_addr[0]~I .oe_sync_reset = "none";
defparam \wr_rd_addr[0]~I .operation_mode = "input";
defparam \wr_rd_addr[0]~I .output_async_reset = "none";
defparam \wr_rd_addr[0]~I .output_power_up = "low";
defparam \wr_rd_addr[0]~I .output_register_mode = "none";
defparam \wr_rd_addr[0]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCCOMB_X21_Y5_N2
cycloneii_lcell_comb \wdata[1]~feeder (
// Equation(s):
// \wdata[1]~feeder_combout  = \wr_data~combout [1]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\wr_data~combout [1]),
	.cin(gnd),
	.combout(\wdata[1]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \wdata[1]~feeder .lut_mask = 16'hFF00;
defparam \wdata[1]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X24_Y6_N8
cycloneii_lcell_comb \waddr[0]~feeder (
// Equation(s):
// \waddr[0]~feeder_combout  = \wr_rd_addr~combout [0]

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\wr_rd_addr~combout [0]),
	.cin(gnd),
	.combout(\waddr[0]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \waddr[0]~feeder .lut_mask = 16'hFF00;
defparam \waddr[0]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at PIN_17
cycloneii_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .oe_power_up = "low";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .operation_mode = "input";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at CLKCTRL_G2
cycloneii_clkctrl \clk~clkctrl (
	.ena(vcc),
	.inclk({gnd,gnd,gnd,\clk~combout }),
	.clkselect(2'b00),
	.devclrn(devclrn),
	.devpor(devpor),
	.outclk(\clk~clkctrl_outclk ));
// synopsys translate_off
defparam \clk~clkctrl .clock_type = "global clock";
defparam \clk~clkctrl .ena_register_mode = "falling edge";
// synopsys translate_on

// atom is at PIN_59
cycloneii_io \spi_sdo~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\spi_sdo~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(spi_sdo));
// synopsys translate_off
defparam \spi_sdo~I .input_async_reset = "none";
defparam \spi_sdo~I .input_power_up = "low";
defparam \spi_sdo~I .input_register_mode = "none";
defparam \spi_sdo~I .input_sync_reset = "none";
defparam \spi_sdo~I .oe_async_reset = "none";
defparam \spi_sdo~I .oe_power_up = "low";
defparam \spi_sdo~I .oe_register_mode = "none";
defparam \spi_sdo~I .oe_sync_reset = "none";
defparam \spi_sdo~I .operation_mode = "input";
defparam \spi_sdo~I .output_async_reset = "none";
defparam \spi_sdo~I .output_power_up = "low";
defparam \spi_sdo~I .output_register_mode = "none";
defparam \spi_sdo~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCCOMB_X19_Y6_N22
cycloneii_lcell_comb \sdo_in~feeder (
// Equation(s):
// \sdo_in~feeder_combout  = \spi_sdo~combout 

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\spi_sdo~combout ),
	.cin(gnd),
	.combout(\sdo_in~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \sdo_in~feeder .lut_mask = 16'hFF00;
defparam \sdo_in~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X19_Y6_N23
cycloneii_lcell_ff sdo_in(
	.clk(\clk~clkctrl_outclk ),
	.datain(\sdo_in~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(\sdo_in~regout ));

// atom is at LCCOMB_X19_Y6_N26
cycloneii_lcell_comb \data_received[0]~feeder (
// Equation(s):
// \data_received[0]~feeder_combout  = \sdo_in~regout 

	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\sdo_in~regout ),
	.cin(gnd),
	.combout(\data_received[0]~feeder_combout ),
	.cout());
// synopsys translate_off
defparam \data_received[0]~feeder .lut_mask = 16'hFF00;
defparam \data_received[0]~feeder .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at PIN_79
cycloneii_io \wr_en~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\wr_en~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(wr_en));
// synopsys translate_off
defparam \wr_en~I .input_async_reset = "none";
defparam \wr_en~I .input_power_up = "low";
defparam \wr_en~I .input_register_mode = "none";
defparam \wr_en~I .input_sync_reset = "none";
defparam \wr_en~I .oe_async_reset = "none";
defparam \wr_en~I .oe_power_up = "low";
defparam \wr_en~I .oe_register_mode = "none";
defparam \wr_en~I .oe_sync_reset = "none";
defparam \wr_en~I .operation_mode = "input";
defparam \wr_en~I .output_async_reset = "none";
defparam \wr_en~I .output_power_up = "low";
defparam \wr_en~I .output_register_mode = "none";
defparam \wr_en~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_86
cycloneii_io \rd_en~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rd_en~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(rd_en));
// synopsys translate_off
defparam \rd_en~I .input_async_reset = "none";
defparam \rd_en~I .input_power_up = "low";
defparam \rd_en~I .input_register_mode = "none";
defparam \rd_en~I .input_sync_reset = "none";
defparam \rd_en~I .oe_async_reset = "none";
defparam \rd_en~I .oe_power_up = "low";
defparam \rd_en~I .oe_register_mode = "none";
defparam \rd_en~I .oe_sync_reset = "none";
defparam \rd_en~I .operation_mode = "input";
defparam \rd_en~I .output_async_reset = "none";
defparam \rd_en~I .output_power_up = "low";
defparam \rd_en~I .output_register_mode = "none";
defparam \rd_en~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LCCOMB_X20_Y6_N2
cycloneii_lcell_comb \always1~0 (
// Equation(s):
// \always1~0_combout  = \wr_en~combout  # \rd_en~combout 

	.dataa(vcc),
	.datab(\wr_en~combout ),
	.datac(vcc),
	.datad(\rd_en~combout ),
	.cin(gnd),
	.combout(\always1~0_combout ),
	.cout());
// synopsys translate_off
defparam \always1~0 .lut_mask = 16'hFFCC;
defparam \always1~0 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X21_Y6_N4
cycloneii_lcell_comb \sck_count~51 (
// Equation(s):
// \sck_count~51_combout  = \main_state.IDLE~regout  & (sck_count[0] $ sck_count[1])

	.dataa(vcc),
	.datab(sck_count[0]),
	.datac(sck_count[1]),
	.datad(\main_state.IDLE~regout ),
	.cin(gnd),
	.combout(\sck_count~51_combout ),
	.cout());
// synopsys translate_off
defparam \sck_count~51 .lut_mask = 16'h3C00;
defparam \sck_count~51 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X21_Y6_N5
cycloneii_lcell_ff \sck_count[1] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\sck_count~51_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(sck_count[1]));

// atom is at LCCOMB_X21_Y6_N24
cycloneii_lcell_comb \Equal1~125 (
// Equation(s):
// \Equal1~125_combout  = !sck_count[1] & sck_count[0]

	.dataa(vcc),
	.datab(vcc),
	.datac(sck_count[1]),
	.datad(sck_count[0]),
	.cin(gnd),
	.combout(\Equal1~125_combout ),
	.cout());
// synopsys translate_off
defparam \Equal1~125 .lut_mask = 16'h0F00;
defparam \Equal1~125 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X20_Y6_N20
cycloneii_lcell_comb \Selector4~62 (
// Equation(s):
// \Selector4~62_combout  = \main_state.IDLE~regout  & (\main_state.START~regout  & !\Equal1~125_combout ) # !\main_state.IDLE~regout  & (\always1~0_combout  # \main_state.START~regout  & !\Equal1~125_combout )

	.dataa(\main_state.IDLE~regout ),
	.datab(\always1~0_combout ),
	.datac(\main_state.START~regout ),
	.datad(\Equal1~125_combout ),
	.cin(gnd),
	.combout(\Selector4~62_combout ),
	.cout());
// synopsys translate_off
defparam \Selector4~62 .lut_mask = 16'h44F4;
defparam \Selector4~62 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at PIN_18
cycloneii_io \resetb~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\resetb~combout ),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(resetb));
// synopsys translate_off
defparam \resetb~I .input_async_reset = "none";