config_dac.vo

Verilog实现 spi接口的FPGA实现 通过仿真

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

// DATE "08/19/2008 14:16:09"

// 
// Device: Altera EP2C5T144C6 Package TQFP144
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module config_dac (
	clk,
	resetb,
	wr_rd_addr,
	wr_en,
	wr_data,
	rd_en,
	rd_data,
	rd_data_valid,
	busy,
	spi_ncs,
	spi_sdio,
	spi_sdo,
	spi_sck);
input 	clk;
input 	resetb;
input 	[4:0] wr_rd_addr;
input 	wr_en;
input 	[7:0] wr_data;
input 	rd_en;
output 	[7:0] rd_data;
output 	rd_data_valid;
output 	busy;
output 	spi_ncs;
output 	spi_sdio;
input 	spi_sdo;
output 	spi_sck;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
// synopsys translate_off
initial $sdf_annotate("config_dac_v.sdo");
// synopsys translate_on

wire \data_to_send[2]~658_combout ;
wire \data_to_send[1]~659_combout ;
wire \data_to_send[0]~660_combout ;
wire \bit_transfered~558_combout ;
wire \data_to_send~908_combout ;
wire \wdata[1]~feeder_combout ;
wire \waddr[0]~feeder_combout ;
wire \clk~combout ;
wire \clk~clkctrl_outclk ;
wire \spi_sdo~combout ;
wire \sdo_in~feeder_combout ;
wire \sdo_in~regout ;
wire \data_received[0]~feeder_combout ;
wire \wr_en~combout ;
wire \rd_en~combout ;
wire \always1~0_combout ;
wire \sck_count~51_combout ;
wire \Equal1~125_combout ;
wire \Selector4~62_combout ;
wire \resetb~combout ;
wire \resetb~clkctrl_outclk ;
wire \main_state.START~regout ;
wire \bit_transfered~557_combout ;
wire \bit_transfered[7]~550_combout ;
wire \bit_transfered~556_combout ;
wire \bit_transfered~555_combout ;
wire \bit_transfered~554_combout ;
wire \bit_transfered~553_combout ;
wire \bit_transfered~549_combout ;
wire \Selector1~58_combout ;
wire \bit_transfered~551_combout ;
wire \Selector1~59_combout ;
wire \main_state.DATA~regout ;
wire \main_state.STOP~49_combout ;
wire \main_state.STOP~regout ;
wire \Selector3~18_combout ;
wire \main_state.IDLE~regout ;
wire \sck_count~50_combout ;
wire \Equal1~126_combout ;
wire \rd_data[0]~reg0feeder_combout ;
wire \read_flag~27_combout ;
wire \read_flag~regout ;
wire \always13~2_combout ;
wire \rd_data[0]~reg0_regout ;
wire \data_received[1]~feeder_combout ;
wire \rd_data[1]~reg0feeder_combout ;
wire \rd_data[1]~reg0_regout ;
wire \data_received[2]~feeder_combout ;
wire \rd_data[2]~reg0feeder_combout ;
wire \rd_data[2]~reg0_regout ;
wire \data_received[3]~feeder_combout ;
wire \rd_data[3]~reg0feeder_combout ;
wire \rd_data[3]~reg0_regout ;
wire \data_received[4]~feeder_combout ;
wire \rd_data[4]~reg0feeder_combout ;
wire \rd_data[4]~reg0_regout ;
wire \data_received[5]~feeder_combout ;
wire \rd_data[5]~reg0feeder_combout ;
wire \rd_data[5]~reg0_regout ;
wire \data_received[6]~feeder_combout ;
wire \rd_data[6]~reg0_regout ;
wire \data_received[7]~feeder_combout ;
wire \rd_data[7]~reg0feeder_combout ;
wire \rd_data[7]~reg0_regout ;
wire \rd_data_valid~reg0_regout ;
wire \busy~reg0feeder_combout ;
wire \busy~reg0_regout ;
wire \spi_ncs~83_combout ;
wire \spi_ncs~84_combout ;
wire \spi_ncs~reg0_regout ;
wire \wdata[7]~feeder_combout ;
wire \bit_transfered~552_combout ;
wire \Selector2~26_combout ;
wire \main_state.INSTRUCTION~regout ;
wire \always9~0_combout ;
wire \wdata[6]~feeder_combout ;
wire \wdata[3]~feeder_combout ;
wire \always9~1_combout ;
wire \data_to_send[3]~657_combout ;
wire \waddr[3]~feeder_combout ;
wire \data_to_send[7]~905_combout ;
wire \data_to_send[4]~656_combout ;
wire \data_to_send~907_combout ;
wire \data_to_send~906_combout ;
wire \data_to_send[7]~655_combout ;
wire \bit_transfered[7]~548_combout ;
wire \spi_sck~33_combout ;
wire \spi_sck~reg0_regout ;
wire [8:0] bit_transfered;
wire [7:0] data_received;
wire [7:0] data_to_send;
wire [1:0] sck_count;
wire [4:0] waddr;
wire [7:0] wdata;
wire [7:0] \wr_data~combout ;
wire [4:0] \wr_rd_addr~combout ;


// atom is at LCFF_X22_Y6_N21
cycloneii_lcell_ff \data_to_send[2] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\data_to_send[2]~658_combout ),
	.sdata(waddr[2]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(\always9~0_combout ),
	.ena(\data_to_send[7]~905_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(data_to_send[2]));

// atom is at LCFF_X22_Y6_N5
cycloneii_lcell_ff \data_to_send[1] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\data_to_send[1]~659_combout ),
	.sdata(waddr[1]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(\always9~0_combout ),
	.ena(\data_to_send[7]~905_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(data_to_send[1]));

// atom is at LCCOMB_X22_Y6_N20
cycloneii_lcell_comb \data_to_send[2]~658 (
// Equation(s):
// \data_to_send[2]~658_combout  = \always9~1_combout  & wdata[2] # !\always9~1_combout  & (data_to_send[1])

	.dataa(wdata[2]),
	.datab(data_to_send[1]),
	.datac(vcc),
	.datad(\always9~1_combout ),
	.cin(gnd),
	.combout(\data_to_send[2]~658_combout ),
	.cout());
// synopsys translate_off
defparam \data_to_send[2]~658 .lut_mask = 16'hAACC;
defparam \data_to_send[2]~658 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X20_Y6_N11
cycloneii_lcell_ff \data_to_send[0] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\data_to_send[0]~660_combout ),
	.sdata(waddr[0]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(\always9~0_combout ),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(data_to_send[0]));

// atom is at LCCOMB_X22_Y6_N4
cycloneii_lcell_comb \data_to_send[1]~659 (
// Equation(s):
// \data_to_send[1]~659_combout  = \always9~1_combout  & (wdata[1]) # !\always9~1_combout  & data_to_send[0]

	.dataa(\always9~1_combout ),
	.datab(data_to_send[0]),
	.datac(vcc),
	.datad(wdata[1]),
	.cin(gnd),
	.combout(\data_to_send[1]~659_combout ),
	.cout());
// synopsys translate_off
defparam \data_to_send[1]~659 .lut_mask = 16'hEE44;
defparam \data_to_send[1]~659 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X20_Y6_N10
cycloneii_lcell_comb \data_to_send[0]~660 (
// Equation(s):
// \data_to_send[0]~660_combout  = \always9~1_combout  & (wdata[0]) # !\always9~1_combout  & \data_to_send~908_combout 

	.dataa(\always9~1_combout ),
	.datab(\data_to_send~908_combout ),
	.datac(vcc),
	.datad(wdata[0]),
	.cin(gnd),
	.combout(\data_to_send[0]~660_combout ),
	.cout());
// synopsys translate_off
defparam \data_to_send[0]~660 .lut_mask = 16'hEE44;
defparam \data_to_send[0]~660 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X21_Y5_N9
cycloneii_lcell_ff \wdata[2] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\wr_data~combout [2]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\wr_en~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(wdata[2]));

// atom is at LCFF_X24_Y6_N13
cycloneii_lcell_ff \waddr[2] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\wr_rd_addr~combout [2]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\always1~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(waddr[2]));

// atom is at LCFF_X22_Y6_N7
cycloneii_lcell_ff \bit_transfered[1] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\bit_transfered~558_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\bit_transfered[7]~550_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(bit_transfered[1]));

// atom is at LCFF_X21_Y5_N3
cycloneii_lcell_ff \wdata[1] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\wdata[1]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\wr_en~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(wdata[1]));

// atom is at LCFF_X24_Y6_N11
cycloneii_lcell_ff \waddr[1] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\wr_rd_addr~combout [1]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\always1~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(waddr[1]));

// atom is at LCCOMB_X22_Y6_N6
cycloneii_lcell_comb \bit_transfered~558 (
// Equation(s):
// \bit_transfered~558_combout  = bit_transfered[0] & (\main_state.IDLE~regout  $ \main_state.START~regout )

	.dataa(vcc),
	.datab(\main_state.IDLE~regout ),
	.datac(\main_state.START~regout ),
	.datad(bit_transfered[0]),
	.cin(gnd),
	.combout(\bit_transfered~558_combout ),
	.cout());
// synopsys translate_off
defparam \bit_transfered~558 .lut_mask = 16'h3C00;
defparam \bit_transfered~558 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCCOMB_X20_Y6_N4
cycloneii_lcell_comb \data_to_send~908 (
// Equation(s):
// \data_to_send~908_combout  = data_to_send[0] & (sck_count[0] # !sck_count[1])

	.dataa(sck_count[1]),
	.datab(vcc),
	.datac(sck_count[0]),
	.datad(data_to_send[0]),
	.cin(gnd),
	.combout(\data_to_send~908_combout ),
	.cout());
// synopsys translate_off
defparam \data_to_send~908 .lut_mask = 16'hF500;
defparam \data_to_send~908 .sum_lutc_input = "datac";
// synopsys translate_on

// atom is at LCFF_X21_Y5_N5
cycloneii_lcell_ff \wdata[0] (
	.clk(\clk~clkctrl_outclk ),
	.datain(gnd),
	.sdata(\wr_data~combout [0]),
	.aclr(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(\wr_en~combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(wdata[0]));

// atom is at LCFF_X24_Y6_N9
cycloneii_lcell_ff \waddr[0] (
	.clk(\clk~clkctrl_outclk ),
	.datain(\waddr[0]~feeder_combout ),
	.sdata(gnd),
	.aclr(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\always1~0_combout ),
	.devclrn(devclrn),
	.devpor(devpor),
	.regout(waddr[0]));

// atom is at PIN_91
cycloneii_io \wr_data[2]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\wr_data~combout [2]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(wr_data[2]));
// synopsys translate_off
defparam \wr_data[2]~I .input_async_reset = "none";
defparam \wr_data[2]~I .input_power_up = "low";
defparam \wr_data[2]~I .input_register_mode = "none";
defparam \wr_data[2]~I .input_sync_reset = "none";
defparam \wr_data[2]~I .oe_async_reset = "none";
defparam \wr_data[2]~I .oe_power_up = "low";
defparam \wr_data[2]~I .oe_register_mode = "none";
defparam \wr_data[2]~I .oe_sync_reset = "none";
defparam \wr_data[2]~I .operation_mode = "input";
defparam \wr_data[2]~I .output_async_reset = "none";
defparam \wr_data[2]~I .output_power_up = "low";
defparam \wr_data[2]~I .output_register_mode = "none";
defparam \wr_data[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_96
cycloneii_io \wr_rd_addr[2]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\wr_rd_addr~combout [2]),
	.regout(),
	.differentialout(),
	.linkout(),
	.padio(wr_rd_addr[2]));
// synopsys translate_off
defparam \wr_rd_addr[2]~I .input_async_reset = "none";
defparam \wr_rd_addr[2]~I .input_power_up = "low";
defparam \wr_rd_addr[2]~I .input_register_mode = "none";
defparam \wr_rd_addr[2]~I .input_sync_reset = "none";
defparam \wr_rd_addr[2]~I .oe_async_reset = "none";
defparam \wr_rd_addr[2]~I .oe_power_up = "low";
defparam \wr_rd_addr[2]~I .oe_register_mode = "none";
defparam \wr_rd_addr[2]~I .oe_sync_reset = "none";
defparam \wr_rd_addr[2]~I .operation_mode = "input";
defparam \wr_rd_addr[2]~I .output_async_reset = "none";
defparam \wr_rd_addr[2]~I .output_power_up = "low";
defparam \wr_rd_addr[2]~I .output_register_mode = "none";
defparam \wr_rd_addr[2]~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_26
cycloneii_io \wr_data[1]~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.differentialin(gnd),
	.linkin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\wr_data~combout [1]),