config_dac.map.summary

Verilog实现 spi接口的FPGA实现 通过仿真

Flow Status : Successful - Tue Aug 19 14:24:23 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : config_dac
Top-level Entity Name : config_dac
Family : Cyclone II
Met timing requirements : N/A
Total logic elements : N/A until Partition Merge
    Total combinational functions : N/A until Partition Merge
    Dedicated logic registers : N/A until Partition Merge
Total registers : N/A until Partition Merge
Total pins : N/A until Partition Merge
Total virtual pins : N/A until Partition Merge
Total memory bits : N/A until Partition Merge
Embedded Multiplier 9-bit elements : N/A until Partition Merge
Total PLLs : N/A until Partition Merge