config_dac.map.rpt

Verilog实现 spi接口的FPGA实现 通过仿真

; Analysis & Elaboration Summary                                                ;
+------------------------------------+------------------------------------------+
; Analysis & Elaboration Status      ; Successful - Tue Aug 19 14:24:23 2008    ;
; Quartus II Version                 ; 7.1 Build 156 04/30/2007 SJ Full Version ;
; Revision Name                      ; config_dac                               ;
; Top-level Entity Name              ; config_dac                               ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; N/A until Partition Merge                ;
;     Total combinational functions  ; N/A until Partition Merge                ;
;     Dedicated logic registers      ; N/A until Partition Merge                ;
; Total registers                    ; N/A until Partition Merge                ;
; Total pins                         ; N/A until Partition Merge                ;
; Total virtual pins                 ; N/A until Partition Merge                ;
; Total memory bits                  ; N/A until Partition Merge                ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                ;
; Total PLLs                         ; N/A until Partition Merge                ;
+------------------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Elaboration Settings                                                                                          ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name                                                          ; config_dac         ; config_dac         ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Type of Retiming Performed During Resynthesis                                  ; Full               ;                    ;
; Resynthesis Optimization Effort                                                ; Normal             ;                    ;
; Physical Synthesis Level for Resynthesis                                       ; Normal             ;                    ;
; Use Generated Physical Constraints File                                        ; On                 ;                    ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |config_dac ;
+----------------+-------+---------------------------------------------------+
; Parameter Name ; Value ; Type                                              ;
+----------------+-------+---------------------------------------------------+
; IDLE           ; 00001 ; Unsigned Binary                                   ;
; START          ; 00010 ; Unsigned Binary                                   ;
; INSTRUCTION    ; 00100 ; Unsigned Binary                                   ;
; DATA           ; 01000 ; Unsigned Binary                                   ;
; STOP           ; 10000 ; Unsigned Binary                                   ;
+----------------+-------+---------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------+
; Analysis & Elaboration Messages ;
+---------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Elaboration
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Tue Aug 19 14:24:23 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off config_dac -c config_dac --analysis_and_elaboration
Info: Found 1 design units, including 1 entities, in source file config_dac.v
    Info: Found entity 1: config_dac
Info: Found 1 design units, including 1 entities, in source file ad9777_spi_interface.v
    Info: Found entity 1: ad9777_spi_interface
Info: Found 1 design units, including 1 entities, in source file test_config_dac.v
    Info: Found entity 1: test_config_dac
Info: Elaborating entity "config_dac" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at config_dac.v(122): truncated value with size 32 to match size of target (2)
Info: Quartus II Analysis & Elaboration was successful. 0 errors, 1 warning
    Info: Allocated 131 megabytes of memory during processing
    Info: Processing ended: Tue Aug 19 14:24:24 2008
    Info: Elapsed time: 00:00:01