soundsample.fit.qmsg

语音采集,直接在QUARTUSII中打开调试.

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0 0 "Finished register packing" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Info: Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "5.132 ns register memory " "Info: Estimated most critical path is register to memory delay of 5.132 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNTER:inst1\|CQI\[12\] 1 REG LAB_X15_Y13 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y13; Fanout = 12; REG Node = 'COUNTER:inst1\|CQI\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "soundsample" "UNKNOWN" "V1" "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/db/soundsample.quartus_db" { Floorplan "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/" "" "" { COUNTER:inst1|CQI[12] } "NODE_NAME" } "" } } { "COUNTER.vhd" "" { Text "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/COUNTER.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.590 ns) 0.961 ns soundram:inst\|altsyncram:altsyncram_component\|altsyncram_i041:auto_generated\|decode_iga:decode3\|w_anode250w\[2\]~8 2 COMB LAB_X16_Y13 208 " "Info: 2: + IC(0.371 ns) + CELL(0.590 ns) = 0.961 ns; Loc. = LAB_X16_Y13; Fanout = 208; COMB Node = 'soundram:inst\|altsyncram:altsyncram_component\|altsyncram_i041:auto_generated\|decode_iga:decode3\|w_anode250w\[2\]~8'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "soundsample" "UNKNOWN" "V1" "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/db/soundsample.quartus_db" { Floorplan "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/" "" "0.961 ns" { COUNTER:inst1|CQI[12] soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|decode_iga:decode3|w_anode250w[2]~8 } "NODE_NAME" } "" } } { "db/decode_iga.tdf" "" { Text "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/db/decode_iga.tdf" 36 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.209 ns) + CELL(0.962 ns) 5.132 ns soundram:inst\|altsyncram:altsyncram_component\|altsyncram_i041:auto_generated\|ram_block1a28~portb_address_reg0 3 MEM M4K_X33_Y5 0 " "Info: 3: + IC(3.209 ns) + CELL(0.962 ns) = 5.132 ns; Loc. = M4K_X33_Y5; Fanout = 0; MEM Node = 'soundram:inst\|altsyncram:altsyncram_component\|altsyncram_i041:auto_generated\|ram_block1a28~portb_address_reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "soundsample" "UNKNOWN" "V1" "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/db/soundsample.quartus_db" { Floorplan "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/" "" "4.171 ns" { soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|decode_iga:decode3|w_anode250w[2]~8 soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a28~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_i041.tdf" "" { Text "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/db/altsyncram_i041.tdf" 613 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.552 ns ( 30.24 % ) " "Info: Total cell delay = 1.552 ns ( 30.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.580 ns ( 69.76 % ) " "Info: Total interconnect delay = 3.580 ns ( 69.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "soundsample" "UNKNOWN" "V1" "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/db/soundsample.quartus_db" { Floorplan "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/" "" "5.132 ns" { COUNTER:inst1|CQI[12] soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|decode_iga:decode3|w_anode250w[2]~8 soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a28~portb_address_reg0 } "NODE_NAME" } "" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 3 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 3%" {  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:08 " "Info: Fitter routing operations ending: elapsed time is 00:00:08" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CS VCC " "Info: Pin CS has VCC driving its datain port" {  } { { "soundsample.bdf" "" { Schematic "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/soundsample.bdf" { { 8 264 440 24 "CS" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CS" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "soundsample" "UNKNOWN" "V1" "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/db/soundsample.quartus_db" { Floorplan "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/" "" "" { CS } "NODE_NAME" } "" } } { "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/soundsample.fld" "" { Floorplan "G:/lzh/教学资料/实验/PLD_EXAM/peixun/soundsample/soundsample.fld" "" "" { CS } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 18 12:23:18 2008 " "Info: Processing ended: Fri Jul 18 12:23:18 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:57 " "Info: Elapsed time: 00:00:57" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}