counter.vhd

来自「语音采集,直接在QUARTUSII中打开调试.」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER IS 
 PORT(LOCK0,CLR : IN STD_LOGIC;
         CLK : IN STD_LOGIC;
          WE : IN STD_LOGIC;
        DOUT : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
       CLKOUT : OUT STD_LOGIC);
END COUNTER;
ARCHITECTURE BEHAV OF COUNTER IS
 SIGNAL CQI : STD_LOGIC_VECTOR(13 DOWNTO 0);
 SIGNAL CLK0 : STD_LOGIC;
BEGIN
 CLK0 <= LOCK0 WHEN WE = '1' ELSE CLK;
PROCESS(CLK0,CLR,CQI)
BEGIN
 IF CLR = '0' THEN CQI <= "00000000000000";
 ELSIF CLK0'EVENT AND CLK0 = '1' THEN CQI <= CQI + 1;
 END IF;
END PROCESS;
 DOUT <= CQI; CLKOUT <=CLK0;
END BEHAV;