altsyncram_n041.tdf

来自「语音采集,直接在QUARTUSII中打开调试.」· TDF 代码 · 共 1,419 行 · 第 1/4 页

TDF
1,419 行
字号
1234
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a51 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a52 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a53 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a54 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a55 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 28671,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a56 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a57 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a58 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a59 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a60 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a61 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a62 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	ram_block1a63 : cyclone_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_CLEAR = "none",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_IN_CLEAR = "none",
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 28672,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 32768,
			PORT_A_LOGICAL_RAM_WIDTH = 8,
			PORT_A_WRITE_ENABLE_CLEAR = "none",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "auto"
		);
	address_a_wire[14..0]	: WIRE;
	clocken0	: NODE;

BEGIN 
	address_reg_a[].CLK = clock0;
	address_reg_a[].D = address_a[14..12];
	address_reg_a[].ENA = clocken0;
	decode3.data[2..0] = address_a_wire[14..12];
	decode3.enable = wren_a;
	deep_decode.data[2..0] = address_a_wire[14..12];
	deep_decode.enable = B"1";
	mux2.data[] = ( ram_block1a[63..0].portadataout[0..0]);
	mux2.sel[] = address_reg_a[].Q;
	ram_block1a[63..0].clk0 = clock0;
	ram_block1a[63..0].ena0 = ( deep_decode.eq[7..7], deep_decode.eq[7..7], deep_decode.eq[7..7], deep_decode.eq[7..7], deep_decode.eq[7..7], deep_decode.eq[7..7], deep_decode.eq[7..7], deep_decode.eq[7..6], deep_decode.eq[6..6], deep_decode.eq[6..6], deep_decode.eq[6..6], deep_decode.eq[6..6], deep_decode.eq[6..6], deep_decode.eq[6..6], deep_decode.eq[6..5], deep_decode.eq[5..5], deep_decode.eq[5..5], deep_decode.eq[5..5], deep_decode.eq[5..5], deep_decode.eq[5..5], deep_decode.eq[5..5], deep_decode.eq[5..4], deep_decode.eq[4..4], deep_decode.eq[4..4], deep_decode.eq[4..4], deep_decode.eq[4..4], deep_decode.eq[4..4], deep_decode.eq[4..4], deep_decode.eq[4..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..3], deep_decode.eq[3..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..2], deep_decode.eq[2..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..1], deep_decode.eq[1..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0], deep_decode.eq[0..0]);
	ram_block1a[63..0].portaaddr[] = ( address_a_wire[11..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[0..0]);
	ram_block1a[9].portadatain[] = ( data_a[1..1]);
	ram_block1a[10].portadatain[] = ( data_a[2..2]);
	ram_block1a[11].portadatain[] = ( data_a[3..3]);
	ram_block1a[12].portadatain[] = ( data_a[4..4]);
	ram_block1a[13].portadatain[] = ( data_a[5..5]);
	ram_block1a[14].portadatain[] = ( data_a[6..6]);
	ram_block1a[15].portadatain[] = ( data_a[7..7]);
	ram_block1a[16].portadatain[] = ( data_a[0..0]);
	ram_block1a[17].portadatain[] = ( data_a[1..1]);
	ram_block1a[18].portadatain[] = ( data_a[2..2]);
	ram_block1a[19].portadatain[] = ( data_a[3..3]);
	ram_block1a[20].portadatain[] = ( data_a[4..4]);
	ram_block1a[21].portadatain[] = ( data_a[5..5]);
	ram_block1a[22].portadatain[] = ( data_a[6..6]);
	ram_block1a[23].portadatain[] = ( data_a[7..7]);
	ram_block1a[24].portadatain[] = ( data_a[0..0]);
	ram_block1a[25].portadatain[] = ( data_a[1..1]);
	ram_block1a[26].portadatain[] = ( data_a[2..2]);
	ram_block1a[27].portadatain[] = ( data_a[3..3]);
	ram_block1a[28].portadatain[] = ( data_a[4..4]);
	ram_block1a[29].portadatain[] = ( data_a[5..5]);
	ram_block1a[30].portadatain[] = ( data_a[6..6]);
	ram_block1a[31].portadatain[] = ( data_a[7..7]);
	ram_block1a[32].portadatain[] = ( data_a[0..0]);
	ram_block1a[33].portadatain[] = ( data_a[1..1]);
	ram_block1a[34].portadatain[] = ( data_a[2..2]);
	ram_block1a[35].portadatain[] = ( data_a[3..3]);
	ram_block1a[36].portadatain[] = ( data_a[4..4]);
	ram_block1a[37].portadatain[] = ( data_a[5..5]);
	ram_block1a[38].portadatain[] = ( data_a[6..6]);
	ram_block1a[39].portadatain[] = ( data_a[7..7]);
	ram_block1a[40].portadatain[] = ( data_a[0..0]);
	ram_block1a[41].portadatain[] = ( data_a[1..1]);
	ram_block1a[42].portadatain[] = ( data_a[2..2]);
	ram_block1a[43].portadatain[] = ( data_a[3..3]);
	ram_block1a[44].portadatain[] = ( data_a[4..4]);
	ram_block1a[45].portadatain[] = ( data_a[5..5]);
	ram_block1a[46].portadatain[] = ( data_a[6..6]);
	ram_block1a[47].portadatain[] = ( data_a[7..7]);
	ram_block1a[48].portadatain[] = ( data_a[0..0]);
	ram_block1a[49].portadatain[] = ( data_a[1..1]);
	ram_block1a[50].portadatain[] = ( data_a[2..2]);
	ram_block1a[51].portadatain[] = ( data_a[3..3]);
	ram_block1a[52].portadatain[] = ( data_a[4..4]);
	ram_block1a[53].portadatain[] = ( data_a[5..5]);
	ram_block1a[54].portadatain[] = ( data_a[6..6]);
	ram_block1a[55].portadatain[] = ( data_a[7..7]);
	ram_block1a[56].portadatain[] = ( data_a[0..0]);
	ram_block1a[57].portadatain[] = ( data_a[1..1]);
	ram_block1a[58].portadatain[] = ( data_a[2..2]);
	ram_block1a[59].portadatain[] = ( data_a[3..3]);
	ram_block1a[60].portadatain[] = ( data_a[4..4]);
	ram_block1a[61].portadatain[] = ( data_a[5..5]);
	ram_block1a[62].portadatain[] = ( data_a[6..6]);
	ram_block1a[63].portadatain[] = ( data_a[7..7]);
	ram_block1a[63..0].portawe = ( decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
	address_a_wire[] = address_a[];
	clocken0 = VCC;
	q_a[] = mux2.result[];
END;
--VALID FILE
1234

altsyncram_n041.tdf - 源码说明

本页面展示了「语音采集,直接在QUARTUSII中打开调试.」中的 altsyncram_n041.tdf 源码文件，采用 TDF 编程语言编写，共 1,419 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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