soundsample.hier_info

语音采集,直接在QUARTUSII中打开调试.

address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[10] => ram_block1a16.PORTAADDR10
address_a[10] => ram_block1a17.PORTAADDR10
address_a[10] => ram_block1a18.PORTAADDR10
address_a[10] => ram_block1a19.PORTAADDR10
address_a[10] => ram_block1a20.PORTAADDR10
address_a[10] => ram_block1a21.PORTAADDR10
address_a[10] => ram_block1a22.PORTAADDR10
address_a[10] => ram_block1a23.PORTAADDR10
address_a[10] => ram_block1a24.PORTAADDR10
address_a[10] => ram_block1a25.PORTAADDR10
address_a[10] => ram_block1a26.PORTAADDR10
address_a[10] => ram_block1a27.PORTAADDR10
address_a[10] => ram_block1a28.PORTAADDR10
address_a[10] => ram_block1a29.PORTAADDR10
address_a[10] => ram_block1a30.PORTAADDR10
address_a[10] => ram_block1a31.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[11] => ram_block1a16.PORTAADDR11
address_a[11] => ram_block1a17.PORTAADDR11
address_a[11] => ram_block1a18.PORTAADDR11
address_a[11] => ram_block1a19.PORTAADDR11
address_a[11] => ram_block1a20.PORTAADDR11
address_a[11] => ram_block1a21.PORTAADDR11
address_a[11] => ram_block1a22.PORTAADDR11
address_a[11] => ram_block1a23.PORTAADDR11
address_a[11] => ram_block1a24.PORTAADDR11
address_a[11] => ram_block1a25.PORTAADDR11
address_a[11] => ram_block1a26.PORTAADDR11
address_a[11] => ram_block1a27.PORTAADDR11
address_a[11] => ram_block1a28.PORTAADDR11
address_a[11] => ram_block1a29.PORTAADDR11
address_a[11] => ram_block1a30.PORTAADDR11
address_a[11] => ram_block1a31.PORTAADDR11
address_a[12] => address_reg_a[0].DATAIN
address_a[12] => decode_iga:decode3.data[0]
address_a[12] => decode_iga:deep_decode.data[0]
address_a[13] => address_reg_a[1].DATAIN
address_a[13] => decode_iga:decode3.data[1]
address_a[13] => decode_iga:deep_decode.data[1]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => address_reg_a[1].CLK
clock0 => address_reg_a[0].CLK
data_a[0] => ram_block1a0.PORTADATAIN
data_a[0] => ram_block1a8.PORTADATAIN
data_a[0] => ram_block1a16.PORTADATAIN
data_a[0] => ram_block1a24.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[1] => ram_block1a9.PORTADATAIN
data_a[1] => ram_block1a17.PORTADATAIN
data_a[1] => ram_block1a25.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[2] => ram_block1a10.PORTADATAIN
data_a[2] => ram_block1a18.PORTADATAIN
data_a[2] => ram_block1a26.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[3] => ram_block1a11.PORTADATAIN
data_a[3] => ram_block1a19.PORTADATAIN
data_a[3] => ram_block1a27.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[4] => ram_block1a12.PORTADATAIN
data_a[4] => ram_block1a20.PORTADATAIN
data_a[4] => ram_block1a28.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[5] => ram_block1a13.PORTADATAIN
data_a[5] => ram_block1a21.PORTADATAIN
data_a[5] => ram_block1a29.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[6] => ram_block1a14.PORTADATAIN
data_a[6] => ram_block1a22.PORTADATAIN
data_a[6] => ram_block1a30.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[7] => ram_block1a15.PORTADATAIN
data_a[7] => ram_block1a23.PORTADATAIN
data_a[7] => ram_block1a31.PORTADATAIN
q_a[0] <= mux_2bb:mux2.result[0]
q_a[1] <= mux_2bb:mux2.result[1]
q_a[2] <= mux_2bb:mux2.result[2]
q_a[3] <= mux_2bb:mux2.result[3]
q_a[4] <= mux_2bb:mux2.result[4]
q_a[5] <= mux_2bb:mux2.result[5]
q_a[6] <= mux_2bb:mux2.result[6]
q_a[7] <= mux_2bb:mux2.result[7]
wren_a => decode_iga:decode3.enable


|soundsample|soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|decode_iga:decode3
data[0] => w_anode234w[1].IN1
data[0] => w_anode250w[1].IN1
data[1] => w_anode242w[2].IN1
data[1] => w_anode250w[2].IN1
enable => w_anode221w[1].IN0
enable => w_anode234w[1].IN0
enable => w_anode242w[1].IN0
enable => w_anode250w[1].IN0
eq[0] <= w_anode221w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode234w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode242w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode250w[2].DB_MAX_OUTPUT_PORT_TYPE


|soundsample|soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|decode_iga:deep_decode
data[0] => w_anode234w[1].IN1
data[0] => w_anode250w[1].IN1
data[1] => w_anode242w[2].IN1
data[1] => w_anode250w[2].IN1
enable => w_anode221w[1].IN0
enable => w_anode234w[1].IN0
enable => w_anode242w[1].IN0
enable => w_anode250w[1].IN0
eq[0] <= w_anode221w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= w_anode234w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[2] <= w_anode242w[2].DB_MAX_OUTPUT_PORT_TYPE
eq[3] <= w_anode250w[2].DB_MAX_OUTPUT_PORT_TYPE


|soundsample|soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE


|soundsample|COUNTER:inst1
LOCK0 => CLK0~0.DATAB
CLR => CQI[12].ACLR
CLR => CQI[11].ACLR
CLR => CQI[10].ACLR
CLR => CQI[9].ACLR
CLR => CQI[8].ACLR
CLR => CQI[7].ACLR
CLR => CQI[6].ACLR
CLR => CQI[5].ACLR
CLR => CQI[4].ACLR
CLR => CQI[3].ACLR
CLR => CQI[2].ACLR
CLR => CQI[1].ACLR
CLR => CQI[0].ACLR
CLR => CQI[13].ACLR
CLK => CLK0~0.DATAA
WE => CLK0~0.OUTPUTSELECT
DOUT[0] <= CQI[0].DB_MAX_OUTPUT_PORT_TYPE
DOUT[1] <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
DOUT[2] <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE
DOUT[3] <= CQI[3].DB_MAX_OUTPUT_PORT_TYPE
DOUT[4] <= CQI[4].DB_MAX_OUTPUT_PORT_TYPE
DOUT[5] <= CQI[5].DB_MAX_OUTPUT_PORT_TYPE
DOUT[6] <= CQI[6].DB_MAX_OUTPUT_PORT_TYPE
DOUT[7] <= CQI[7].DB_MAX_OUTPUT_PORT_TYPE
DOUT[8] <= CQI[8].DB_MAX_OUTPUT_PORT_TYPE
DOUT[9] <= CQI[9].DB_MAX_OUTPUT_PORT_TYPE
DOUT[10] <= CQI[10].DB_MAX_OUTPUT_PORT_TYPE
DOUT[11] <= CQI[11].DB_MAX_OUTPUT_PORT_TYPE
DOUT[12] <= CQI[12].DB_MAX_OUTPUT_PORT_TYPE
DOUT[13] <= CQI[13].DB_MAX_OUTPUT_PORT_TYPE
CLKOUT <= CLK0~0.DB_MAX_OUTPUT_PORT_TYPE