📄 decode_iga.tdf
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ VERSION_END
-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 4
SUBDESIGN decode_iga
(
data[1..0] : input;
enable : input;
eq[3..0] : output;
)
VARIABLE
data_wire[1..0] : WIRE;
enable_wire : WIRE;
eq_node[3..0] : WIRE;
eq_wire[3..0] : WIRE;
w_anode221w[2..0] : WIRE;
w_anode234w[2..0] : WIRE;
w_anode242w[2..0] : WIRE;
w_anode250w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[3..0] = eq_wire[3..0];
eq_wire[] = ( w_anode250w[2..2], w_anode242w[2..2], w_anode234w[2..2], w_anode221w[2..2]);
w_anode221w[] = ( (w_anode221w[1..1] & (! data_wire[1..1])), (w_anode221w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode234w[] = ( (w_anode234w[1..1] & (! data_wire[1..1])), (w_anode234w[0..0] & data_wire[0..0]), enable_wire);
w_anode242w[] = ( (w_anode242w[1..1] & data_wire[1..1]), (w_anode242w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode250w[] = ( (w_anode250w[1..1] & data_wire[1..1]), (w_anode250w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE
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