altsyncram_iv51.tdf

语音采集,直接在QUARTUSII中打开调试.

--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" ENABLE_RUNTIME_MOD="YES" INDATA_ACLR_A="NONE" INSTANCE_NAME="ram1" LOW_POWER_MODE="AUTO" NUMWORDS_A=65536 OPERATION_MODE="SINGLE_PORT" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=16 WRCONTROL_ACLR_A="NONE" address_a clock0 data_a q_a wren_a
--VERSION_BEGIN 5.1 cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION altsyncram_1pb2 (address_a[15..0], address_b[15..0], clock0, clock1, data_a[7..0], data_b[7..0], wren_a, wren_b)
RETURNS ( q_a[7..0], q_b[7..0]);
FUNCTION sld_mod_ram_rom (data_read[7..0])
WITH ( 	CVALUE,	IS_DATA_IN_RAM,	IS_READABLE,	NODE_NAME,	NUMWORDS,	SHIFT_COUNT_BITS,	WIDTH_WORD,	WIDTHAD) 
RETURNS ( address[15..0], data_write[7..0], enable_write, tck_usr);

--synthesis_resources = lut 106 M4K 2048 sld_mod_ram_rom 1 
SUBDESIGN altsyncram_iv51
( 
	address_a[15..0]	:	input;
	clock0	:	input;
	data_a[7..0]	:	input;
	q_a[7..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	altsyncram1 : altsyncram_1pb2;
	mgl_prim2 : sld_mod_ram_rom
		WITH (
			CVALUE = "00000000",
			IS_DATA_IN_RAM = 1,
			IS_READABLE = 1,
			NODE_NAME = 1918987569,
			NUMWORDS = 65536,
			SHIFT_COUNT_BITS = 4,
			WIDTH_WORD = 8,
			WIDTHAD = 16
		);

BEGIN 
	altsyncram1.address_a[] = address_a[];
	altsyncram1.address_b[] = mgl_prim2.address[];
	altsyncram1.clock0 = clock0;
	altsyncram1.clock1 = mgl_prim2.tck_usr;
	altsyncram1.data_a[] = data_a[];
	altsyncram1.data_b[] = mgl_prim2.data_write[];
	altsyncram1.wren_a = wren_a;
	altsyncram1.wren_b = mgl_prim2.enable_write;
	mgl_prim2.data_read[] = altsyncram1.q_b[];
	q_a[] = altsyncram1.q_a[];
END;
--VALID FILE