soundsample.tan.rpt

语音采集,直接在QUARTUSII中打开调试.

; Clock Hold: 'CLK'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; COUNTER:inst1|CQI[13]                                                                                          ; COUNTER:inst1|CQI[13]                                                                                   ; CLK        ; CLK      ; 40           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                                                ;                                                                                                         ;            ;          ; 40           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; WREN            ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                  ; To                                                                                                             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------+----------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 97.51 MHz ( period = 10.255 ns )                    ; COUNTER:inst1|CQI[13] ; soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a0~porta_address_reg11  ; CLK        ; CLK      ; None                        ; None                      ; 7.808 ns                ;
; N/A                                     ; 97.51 MHz ( period = 10.255 ns )                    ; COUNTER:inst1|CQI[13] ; soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a0~porta_address_reg10  ; CLK        ; CLK      ; None                        ; None                      ; 7.808 ns                ;
; N/A                                     ; 97.51 MHz ( period = 10.255 ns )                    ; COUNTER:inst1|CQI[13] ; soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a0~porta_address_reg9   ; CLK        ; CLK      ; None                        ; None                      ; 7.808 ns                ;
; N/A                                     ; 97.51 MHz ( period = 10.255 ns )                    ; COUNTER:inst1|CQI[13] ; soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a0~porta_address_reg8   ; CLK        ; CLK      ; None                        ; None                      ; 7.808 ns                ;
; N/A                                     ; 97.51 MHz ( period = 10.255 ns )                    ; COUNTER:inst1|CQI[13] ; soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a0~porta_address_reg7   ; CLK        ; CLK      ; None                        ; None                      ; 7.808 ns                ;
; N/A                                     ; 97.51 MHz ( period = 10.255 ns )                    ; COUNTER:inst1|CQI[13] ; soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a0~porta_address_reg6   ; CLK        ; CLK      ; None                        ; None                      ; 7.808 ns                ;