soundsample.map.eqn

语音采集,直接在QUARTUSII中打开调试.

F1_ram_block1a8_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a8_PORT_A_address_reg = DFFE(F1_ram_block1a8_PORT_A_address, F1_ram_block1a8_clock_0, , , F1_ram_block1a8_clock_enable_0);
F1_ram_block1a8_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a8_PORT_B_address_reg = DFFE(F1_ram_block1a8_PORT_B_address, F1_ram_block1a8_clock_0, , , F1_ram_block1a8_clock_enable_0);
F1_ram_block1a8_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a8_PORT_A_write_enable_reg = DFFE(F1_ram_block1a8_PORT_A_write_enable, F1_ram_block1a8_clock_0, , , F1_ram_block1a8_clock_enable_0);
F1_ram_block1a8_clock_0 = C1L1;
F1_ram_block1a8_clock_enable_0 = G1L6;
F1_ram_block1a8_PORT_A_data_out = MEMORY(F1_ram_block1a8_PORT_A_data_in_reg, , F1_ram_block1a8_PORT_A_address_reg, F1_ram_block1a8_PORT_B_address_reg, F1_ram_block1a8_PORT_A_write_enable_reg, , , , F1_ram_block1a8_clock_0, , F1_ram_block1a8_clock_enable_0, , , );
F1_ram_block1a8 = F1_ram_block1a8_PORT_A_data_out[0];


--F1_ram_block1a0 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a0
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a0_PORT_A_data_in = D1_datain[0];
F1_ram_block1a0_PORT_A_data_in_reg = DFFE(F1_ram_block1a0_PORT_A_data_in, F1_ram_block1a0_clock_0, , , F1_ram_block1a0_clock_enable_0);
F1_ram_block1a0_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a0_PORT_A_address_reg = DFFE(F1_ram_block1a0_PORT_A_address, F1_ram_block1a0_clock_0, , , F1_ram_block1a0_clock_enable_0);
F1_ram_block1a0_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a0_PORT_B_address_reg = DFFE(F1_ram_block1a0_PORT_B_address, F1_ram_block1a0_clock_0, , , F1_ram_block1a0_clock_enable_0);
F1_ram_block1a0_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a0_PORT_A_write_enable_reg = DFFE(F1_ram_block1a0_PORT_A_write_enable, F1_ram_block1a0_clock_0, , , F1_ram_block1a0_clock_enable_0);
F1_ram_block1a0_clock_0 = C1L1;
F1_ram_block1a0_clock_enable_0 = G1L3;
F1_ram_block1a0_PORT_A_data_out = MEMORY(F1_ram_block1a0_PORT_A_data_in_reg, , F1_ram_block1a0_PORT_A_address_reg, F1_ram_block1a0_PORT_B_address_reg, F1_ram_block1a0_PORT_A_write_enable_reg, , , , F1_ram_block1a0_clock_0, , F1_ram_block1a0_clock_enable_0, , , );
F1_ram_block1a0 = F1_ram_block1a0_PORT_A_data_out[0];


--H1L1 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[0]~366
--operation mode is normal

H1L1 = F1_address_reg_a[1] & (F1_address_reg_a[0]) # !F1_address_reg_a[1] & (F1_address_reg_a[0] & F1_ram_block1a8 # !F1_address_reg_a[0] & (F1_ram_block1a0));


--F1_ram_block1a24 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a24
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a24_PORT_A_data_in = D1_datain[0];
F1_ram_block1a24_PORT_A_data_in_reg = DFFE(F1_ram_block1a24_PORT_A_data_in, F1_ram_block1a24_clock_0, , , F1_ram_block1a24_clock_enable_0);
F1_ram_block1a24_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a24_PORT_A_address_reg = DFFE(F1_ram_block1a24_PORT_A_address, F1_ram_block1a24_clock_0, , , F1_ram_block1a24_clock_enable_0);
F1_ram_block1a24_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a24_PORT_B_address_reg = DFFE(F1_ram_block1a24_PORT_B_address, F1_ram_block1a24_clock_0, , , F1_ram_block1a24_clock_enable_0);
F1_ram_block1a24_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a24_PORT_A_write_enable_reg = DFFE(F1_ram_block1a24_PORT_A_write_enable, F1_ram_block1a24_clock_0, , , F1_ram_block1a24_clock_enable_0);
F1_ram_block1a24_clock_0 = C1L1;
F1_ram_block1a24_clock_enable_0 = G1L12;
F1_ram_block1a24_PORT_A_data_out = MEMORY(F1_ram_block1a24_PORT_A_data_in_reg, , F1_ram_block1a24_PORT_A_address_reg, F1_ram_block1a24_PORT_B_address_reg, F1_ram_block1a24_PORT_A_write_enable_reg, , , , F1_ram_block1a24_clock_0, , F1_ram_block1a24_clock_enable_0, , , );
F1_ram_block1a24 = F1_ram_block1a24_PORT_A_data_out[0];


--H1L2 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[0]~367
--operation mode is normal

H1L2 = F1_address_reg_a[1] & (H1L1 & (F1_ram_block1a24) # !H1L1 & F1_ram_block1a16) # !F1_address_reg_a[1] & (H1L1);


--D1_present_state.swait is ad0809:inst2|present_state.swait
--operation mode is normal

D1_present_state.swait_lut_out = D1_present_state.write # D1_present_state.swait & INT;
D1_present_state.swait = DFFEAS(D1_present_state.swait_lut_out, CLK, CLR, , , , , , );


--D1_present_state.idle is ad0809:inst2|present_state.idle
--operation mode is normal

D1_present_state.idle_lut_out = !D1_present_state.slock;
D1_present_state.idle = DFFEAS(D1_present_state.idle_lut_out, CLK, CLR, , , , , , );


--C1_CQI[12] is COUNTER:inst1|CQI[12]
--operation mode is arithmetic

C1_CQI[12]_carry_eqn = C1L26;
C1_CQI[12]_lut_out = C1_CQI[12] $ (!C1_CQI[12]_carry_eqn);
C1_CQI[12] = DFFEAS(C1_CQI[12]_lut_out, C1L1, CLR, , , , , , );

--C1L28 is COUNTER:inst1|CQI[12]~113
--operation mode is arithmetic

C1L28 = CARRY(C1_CQI[12] & (!C1L26));


--C1_CQI[13] is COUNTER:inst1|CQI[13]
--operation mode is normal

C1_CQI[13]_carry_eqn = C1L28;
C1_CQI[13]_lut_out = C1_CQI[13] $ (C1_CQI[13]_carry_eqn);
C1_CQI[13] = DFFEAS(C1_CQI[13]_lut_out, C1L1, CLR, , , , , , );


--G1_w_anode234w[2] is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|decode_iga:decode3|w_anode234w[2]
--operation mode is normal

G1_w_anode234w[2] = C1_CQI[12] & WREN & (!C1_CQI[13]);


--C1L1 is COUNTER:inst1|CLKOUT~7
--operation mode is normal

C1L1 = WREN & D1_present_state.slock # !WREN & (CLK);


--G1L6 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|decode_iga:decode3|w_anode234w[2]~9
--operation mode is normal

G1L6 = C1_CQI[12] & (!C1_CQI[13]);


--D1_datain[7] is ad0809:inst2|datain[7]
--operation mode is normal

D1_datain[7]_lut_out = D[7];
D1_datain[7] = DFFEAS(D1_datain[7]_lut_out, D1_present_state.slock, VCC, , , , , , );


--C1_CQI[0] is COUNTER:inst1|CQI[0]
--operation mode is arithmetic

C1_CQI[0]_lut_out = !C1_CQI[0];
C1_CQI[0] = DFFEAS(C1_CQI[0]_lut_out, C1L1, CLR, , , , , , );

--C1L4 is COUNTER:inst1|CQI[0]~121
--operation mode is arithmetic

C1L4 = CARRY(C1_CQI[0]);


--C1_CQI[1] is COUNTER:inst1|CQI[1]
--operation mode is arithmetic

C1_CQI[1]_carry_eqn = C1L4;
C1_CQI[1]_lut_out = C1_CQI[1] $ (C1_CQI[1]_carry_eqn);
C1_CQI[1] = DFFEAS(C1_CQI[1]_lut_out, C1L1, CLR, , , , , , );

--C1L6 is COUNTER:inst1|CQI[1]~125
--operation mode is arithmetic

C1L6 = CARRY(!C1L4 # !C1_CQI[1]);


--C1_CQI[2] is COUNTER:inst1|CQI[2]
--operation mode is arithmetic

C1_CQI[2]_carry_eqn = C1L6;
C1_CQI[2]_lut_out = C1_CQI[2] $ (!C1_CQI[2]_carry_eqn);
C1_CQI[2] = DFFEAS(C1_CQI[2]_lut_out, C1L1, CLR, , , , , , );

--C1L8 is COUNTER:inst1|CQI[2]~129
--operation mode is arithmetic

C1L8 = CARRY(C1_CQI[2] & (!C1L6));


--C1_CQI[3] is COUNTER:inst1|CQI[3]
--operation mode is arithmetic

C1_CQI[3]_carry_eqn = C1L8;
C1_CQI[3]_lut_out = C1_CQI[3] $ (C1_CQI[3]_carry_eqn);
C1_CQI[3] = DFFEAS(C1_CQI[3]_lut_out, C1L1, CLR, , , , , , );

--C1L10 is COUNTER:inst1|CQI[3]~133
--operation mode is arithmetic

C1L10