soundsample.map.eqn

语音采集,直接在QUARTUSII中打开调试.

F1_ram_block1a10_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a10_PORT_B_address_reg = DFFE(F1_ram_block1a10_PORT_B_address, F1_ram_block1a10_clock_0, , , F1_ram_block1a10_clock_enable_0);
F1_ram_block1a10_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a10_PORT_A_write_enable_reg = DFFE(F1_ram_block1a10_PORT_A_write_enable, F1_ram_block1a10_clock_0, , , F1_ram_block1a10_clock_enable_0);
F1_ram_block1a10_clock_0 = C1L1;
F1_ram_block1a10_clock_enable_0 = G1L6;
F1_ram_block1a10_PORT_A_data_out = MEMORY(F1_ram_block1a10_PORT_A_data_in_reg, , F1_ram_block1a10_PORT_A_address_reg, F1_ram_block1a10_PORT_B_address_reg, F1_ram_block1a10_PORT_A_write_enable_reg, , , , F1_ram_block1a10_clock_0, , F1_ram_block1a10_clock_enable_0, , , );
F1_ram_block1a10 = F1_ram_block1a10_PORT_A_data_out[0];


--F1_ram_block1a2 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a2
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a2_PORT_A_data_in = D1_datain[2];
F1_ram_block1a2_PORT_A_data_in_reg = DFFE(F1_ram_block1a2_PORT_A_data_in, F1_ram_block1a2_clock_0, , , F1_ram_block1a2_clock_enable_0);
F1_ram_block1a2_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a2_PORT_A_address_reg = DFFE(F1_ram_block1a2_PORT_A_address, F1_ram_block1a2_clock_0, , , F1_ram_block1a2_clock_enable_0);
F1_ram_block1a2_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a2_PORT_B_address_reg = DFFE(F1_ram_block1a2_PORT_B_address, F1_ram_block1a2_clock_0, , , F1_ram_block1a2_clock_enable_0);
F1_ram_block1a2_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a2_PORT_A_write_enable_reg = DFFE(F1_ram_block1a2_PORT_A_write_enable, F1_ram_block1a2_clock_0, , , F1_ram_block1a2_clock_enable_0);
F1_ram_block1a2_clock_0 = C1L1;
F1_ram_block1a2_clock_enable_0 = G1L3;
F1_ram_block1a2_PORT_A_data_out = MEMORY(F1_ram_block1a2_PORT_A_data_in_reg, , F1_ram_block1a2_PORT_A_address_reg, F1_ram_block1a2_PORT_B_address_reg, F1_ram_block1a2_PORT_A_write_enable_reg, , , , F1_ram_block1a2_clock_0, , F1_ram_block1a2_clock_enable_0, , , );
F1_ram_block1a2 = F1_ram_block1a2_PORT_A_data_out[0];


--H1L5 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[2]~362
--operation mode is normal

H1L5 = F1_address_reg_a[1] & (F1_address_reg_a[0]) # !F1_address_reg_a[1] & (F1_address_reg_a[0] & F1_ram_block1a10 # !F1_address_reg_a[0] & (F1_ram_block1a2));


--F1_ram_block1a26 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a26
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a26_PORT_A_data_in = D1_datain[2];
F1_ram_block1a26_PORT_A_data_in_reg = DFFE(F1_ram_block1a26_PORT_A_data_in, F1_ram_block1a26_clock_0, , , F1_ram_block1a26_clock_enable_0);
F1_ram_block1a26_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a26_PORT_A_address_reg = DFFE(F1_ram_block1a26_PORT_A_address, F1_ram_block1a26_clock_0, , , F1_ram_block1a26_clock_enable_0);
F1_ram_block1a26_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a26_PORT_B_address_reg = DFFE(F1_ram_block1a26_PORT_B_address, F1_ram_block1a26_clock_0, , , F1_ram_block1a26_clock_enable_0);
F1_ram_block1a26_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a26_PORT_A_write_enable_reg = DFFE(F1_ram_block1a26_PORT_A_write_enable, F1_ram_block1a26_clock_0, , , F1_ram_block1a26_clock_enable_0);
F1_ram_block1a26_clock_0 = C1L1;
F1_ram_block1a26_clock_enable_0 = G1L12;
F1_ram_block1a26_PORT_A_data_out = MEMORY(F1_ram_block1a26_PORT_A_data_in_reg, , F1_ram_block1a26_PORT_A_address_reg, F1_ram_block1a26_PORT_B_address_reg, F1_ram_block1a26_PORT_A_write_enable_reg, , , , F1_ram_block1a26_clock_0, , F1_ram_block1a26_clock_enable_0, , , );
F1_ram_block1a26 = F1_ram_block1a26_PORT_A_data_out[0];


--H1L6 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[2]~363
--operation mode is normal

H1L6 = F1_address_reg_a[1] & (H1L5 & (F1_ram_block1a26) # !H1L5 & F1_ram_block1a18) # !F1_address_reg_a[1] & (H1L5);


--F1_ram_block1a9 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a9
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a9_PORT_A_data_in = D1_datain[1];
F1_ram_block1a9_PORT_A_data_in_reg = DFFE(F1_ram_block1a9_PORT_A_data_in, F1_ram_block1a9_clock_0, , , F1_ram_block1a9_clock_enable_0);
F1_ram_block1a9_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a9_PORT_A_address_reg = DFFE(F1_ram_block1a9_PORT_A_address, F1_ram_block1a9_clock_0, , , F1_ram_block1a9_clock_enable_0);
F1_ram_block1a9_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a9_PORT_B_address_reg = DFFE(F1_ram_block1a9_PORT_B_address, F1_ram_block1a9_clock_0, , , F1_ram_block1a9_clock_enable_0);
F1_ram_block1a9_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a9_PORT_A_write_enable_reg = DFFE(F1_ram_block1a9_PORT_A_write_enable, F1_ram_block1a9_clock_0, , , F1_ram_block1a9_clock_enable_0);
F1_ram_block1a9_clock_0 = C1L1;
F1_ram_block1a9_clock_enable_0 = G1L6;
F1_ram_block1a9_PORT_A_data_out = MEMORY(F1_ram_block1a9_PORT_A_data_in_reg, , F1_ram_block1a9_PORT_A_address_reg, F1_ram_block1a9_PORT_B_address_reg, F1_ram_block1a9_PORT_A_write_enable_reg, , , , F1_ram_block1a9_clock_0, , F1_ram_block1a9_clock_enable_0, , , );
F1_ram_block1a9 = F1_ram_block1a9_PORT_A_data_out[0];


--F1_ram_block1a17 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a17
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a17_PORT_A_data_in = D1_datain[1];
F1_ram_block1a17_PORT_A_data_in_reg = DFFE(F1_ram_block1a17_PORT_A_data_in, F1_ram_block1a17_clock_0, , , F1_ram_block1a17_clock_enable_0);
F1_ram_block1a17_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a17_PORT_A_address_reg = DFFE(F1_ram_block1a17_PORT_A_address, F1_ram_block1a17_clock_0, , , F1_ram_block1a17_clock_enable_0);
F1_ram_block1a17_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a17_PORT_B_address_reg = DFFE(F1_ram_block1a17_PORT_B_address, F1_ram_block1a17_clock_0, , , F1_ram_block1a17_clock_enable_0);
F1_ram_block1a17_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a17_PORT_A_write_enable_reg = DFFE(F1_ram_block1a17_PORT_A_write_enable, F1_ram_block1a17_clock_0, , , F1_ram_block1a17_clock_enable_0);
F1_ram_block1a17_clock_0 = C1L1;
F1_ram_block1a17_clock_enable_0 = G1L9;
F1_ram_block1a17_PORT_A_data_out = MEMORY(F1_ram_block1a17_PORT_A_data_in_reg, , F1_ram_block1a17_PORT_A_address_reg, F1_ram_block1a17_PORT_B_address_reg, F1_ram_block1a17_PORT_A_write_enable_reg, , , , F1_ram_block1a17_clock_0, , F1_ram_block1a17_clock_enable_0, , , );
F1_ram_block1a17 = F1_ram_block1a17_PORT_A_data_out[0];


--F1_ram_block1a1 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a1
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a1_PORT_A_data_in = D1_datain[1];
F1_ram_block1a1_PORT_A_data_in_reg = DFFE(F1_ram_block1a1_PORT_A_data_in, F1_ram_block1a1_clock_0, , , F1_ram_block1a1_clock_enable_0);
F1_ram_block1a1_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a1_PORT_A_address_reg = DFFE(F1_ram_block1a1_PORT_A_address, F1_ram_block1a1_clock_0, , , F1_ram_block1a1_clock_enable_0);
F1_ram_block1a1_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a1_PORT_B_address_reg = DFFE(F1_ram_block1a1_PORT_B_address, F1_ram_block1a1_clock_0, , , F1_ram_block1a1_clock_enable_0);
F1_ram_block1a1_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a1_PORT_A_write_enable_reg = DFFE(F1_ram_block1a1_PORT_A_write_enable, F1_ram_block1a1_clock_0, , , F1_ram_block1a1_clock_enable_0);
F1_ram_block1a1_clock_0 = C1L1;
F1_ram_block1a1_clock_enable_0 = G1L3;
F1_ram_block1a1_PORT_A_data_out = MEMORY(F1_ram_block1a1_PORT_A_data_in_reg, , F1_ram_block1a1_PORT_A_address_reg, F1_ram_block1a1_PORT_B_address_reg, F1_ram_block1a1_PORT_A_write_enable_reg, , , , F1_ram_block1a1_clock_0, , F1_ram_block1a1_clock_enable_0, , , );
F1_ram_block1a1 = F1_ram_block1a1_PORT_A_data_out[0];


--H1L3 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[1]~364
--operation mode is normal

H1L3 = F1_address_reg_a[0] & (F1_address_reg_a[1]) # !F1_address_reg_a[0] & (F1_address_reg_a[1] & F1_ram_block1a17 # !F1_address_reg_a[1] & (F1_ram_block1a1));


--F1_ram_block1a25 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a25
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a25_PORT_A_data_in = D1_datain[1];
F1_ram_block1a25_PORT_A_data_in_reg = DFFE(F1_ram_block1a25_PORT_A_data_in, F1_ram_block1a25_clock_0, , , F1_ram_block1a25_clock_enable_0);
F1_ram_block1a25_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a25_PORT_A_address_reg = DFFE(F1_ram_block1a25_PORT_A_address, F1_ram_block1a25_clock_0, , , F1_ram_block1a25_clock_enable_0);
F1_ram_block1a25_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a25_PORT_B_address_reg = DFFE(F1_ram_block1a25_PORT_B_address, F1_ram_block1a25_clock_0, , , F1_ram_block1a25_clock_enable_0);
F1_ram_block1a25_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a25_PORT_A_write_enable_reg = DFFE(F1_ram_block1a25_PORT_A_write_enable, F1_ram_block1a25_clock_0, , , F1_ram_block1a25_clock_enable_0);
F1_ram_block1a25_clock_0 = C1L1;
F1_ram_block1a25_clock_enable_0 = G1L12;
F1_ram_block1a25_PORT_A_data_out = MEMORY(F1_ram_block1a25_PORT_A_data_in_reg, , F1_ram_block1a25_PORT_A_address_reg, F1_ram_block1a25_PORT_B_address_reg, F1_ram_block1a25_PORT_A_write_enable_reg, , , , F1_ram_block1a25_clock_0, , F1_ram_block1a25_clock_enable_0, , , );
F1_ram_block1a25 = F1_ram_block1a25_PORT_A_data_out[0];


--H1L4 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[1]~365
--operation mode is normal

H1L4 = F1_address_reg_a[0] & (H1L3 & (F1_ram_block1a25) # !H1L3 & F1_ram_block1a9) # !F1_address_reg_a[0] & (H1L3);


--F1_ram_block1a16 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a16
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a16_PORT_A_data_in = D1_datain[0];
F1_ram_block1a16_PORT_A_data_in_reg = DFFE(F1_ram_block1a16_PORT_A_data_in, F1_ram_block1a16_clock_0, , , F1_ram_block1a16_clock_enable_0);
F1_ram_block1a16_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a16_PORT_A_address_reg = DFFE(F1_ram_block1a16_PORT_A_address, F1_ram_block1a16_clock_0, , , F1_ram_block1a16_clock_enable_0);
F1_ram_block1a16_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a16_PORT_B_address_reg = DFFE(F1_ram_block1a16_PORT_B_address, F1_ram_block1a16_clock_0, , , F1_ram_block1a16_clock_enable_0);
F1_ram_block1a16_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a16_PORT_A_write_enable_reg = DFFE(F1_ram_block1a16_PORT_A_write_enable, F1_ram_block1a16_clock_0, , , F1_ram_block1a16_clock_enable_0);
F1_ram_block1a16_clock_0 = C1L1;
F1_ram_block1a16_clock_enable_0 = G1L9;
F1_ram_block1a16_PORT_A_data_out = MEMORY(F1_ram_block1a16_PORT_A_data_in_reg, , F1_ram_block1a16_PORT_A_address_reg, F1_ram_block1a16_PORT_B_address_reg, F1_ram_block1a16_PORT_A_write_enable_reg, , , , F1_ram_block1a16_clock_0, , F1_ram_block1a16_clock_enable_0, , , );
F1_ram_block1a16 = F1_ram_block1a16_PORT_A_data_out[0];


--F1_ram_block1a8 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a8
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a8_PORT_A_data_in = D1_datain[0];
F1_ram_block1a8_PORT_A_data_in_reg = DFFE(F1_ram_block1a8_PORT_A_data_in, F1_ram_block1a8_clock_0, , , F1_ram_block1a8_clock_enable_0);