soundsample.map.eqn

语音采集,直接在QUARTUSII中打开调试.

F1_ram_block1a12_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a12_PORT_A_write_enable_reg = DFFE(F1_ram_block1a12_PORT_A_write_enable, F1_ram_block1a12_clock_0, , , F1_ram_block1a12_clock_enable_0);
F1_ram_block1a12_clock_0 = C1L1;
F1_ram_block1a12_clock_enable_0 = G1L6;
F1_ram_block1a12_PORT_A_data_out = MEMORY(F1_ram_block1a12_PORT_A_data_in_reg, , F1_ram_block1a12_PORT_A_address_reg, F1_ram_block1a12_PORT_B_address_reg, F1_ram_block1a12_PORT_A_write_enable_reg, , , , F1_ram_block1a12_clock_0, , F1_ram_block1a12_clock_enable_0, , , );
F1_ram_block1a12 = F1_ram_block1a12_PORT_A_data_out[0];


--F1_ram_block1a4 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a4
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a4_PORT_A_data_in = D1_datain[4];
F1_ram_block1a4_PORT_A_data_in_reg = DFFE(F1_ram_block1a4_PORT_A_data_in, F1_ram_block1a4_clock_0, , , F1_ram_block1a4_clock_enable_0);
F1_ram_block1a4_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a4_PORT_A_address_reg = DFFE(F1_ram_block1a4_PORT_A_address, F1_ram_block1a4_clock_0, , , F1_ram_block1a4_clock_enable_0);
F1_ram_block1a4_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a4_PORT_B_address_reg = DFFE(F1_ram_block1a4_PORT_B_address, F1_ram_block1a4_clock_0, , , F1_ram_block1a4_clock_enable_0);
F1_ram_block1a4_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a4_PORT_A_write_enable_reg = DFFE(F1_ram_block1a4_PORT_A_write_enable, F1_ram_block1a4_clock_0, , , F1_ram_block1a4_clock_enable_0);
F1_ram_block1a4_clock_0 = C1L1;
F1_ram_block1a4_clock_enable_0 = G1L3;
F1_ram_block1a4_PORT_A_data_out = MEMORY(F1_ram_block1a4_PORT_A_data_in_reg, , F1_ram_block1a4_PORT_A_address_reg, F1_ram_block1a4_PORT_B_address_reg, F1_ram_block1a4_PORT_A_write_enable_reg, , , , F1_ram_block1a4_clock_0, , F1_ram_block1a4_clock_enable_0, , , );
F1_ram_block1a4 = F1_ram_block1a4_PORT_A_data_out[0];


--H1L9 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[4]~358
--operation mode is normal

H1L9 = F1_address_reg_a[1] & (F1_address_reg_a[0]) # !F1_address_reg_a[1] & (F1_address_reg_a[0] & F1_ram_block1a12 # !F1_address_reg_a[0] & (F1_ram_block1a4));


--F1_ram_block1a28 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a28
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a28_PORT_A_data_in = D1_datain[4];
F1_ram_block1a28_PORT_A_data_in_reg = DFFE(F1_ram_block1a28_PORT_A_data_in, F1_ram_block1a28_clock_0, , , F1_ram_block1a28_clock_enable_0);
F1_ram_block1a28_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a28_PORT_A_address_reg = DFFE(F1_ram_block1a28_PORT_A_address, F1_ram_block1a28_clock_0, , , F1_ram_block1a28_clock_enable_0);
F1_ram_block1a28_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a28_PORT_B_address_reg = DFFE(F1_ram_block1a28_PORT_B_address, F1_ram_block1a28_clock_0, , , F1_ram_block1a28_clock_enable_0);
F1_ram_block1a28_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a28_PORT_A_write_enable_reg = DFFE(F1_ram_block1a28_PORT_A_write_enable, F1_ram_block1a28_clock_0, , , F1_ram_block1a28_clock_enable_0);
F1_ram_block1a28_clock_0 = C1L1;
F1_ram_block1a28_clock_enable_0 = G1L12;
F1_ram_block1a28_PORT_A_data_out = MEMORY(F1_ram_block1a28_PORT_A_data_in_reg, , F1_ram_block1a28_PORT_A_address_reg, F1_ram_block1a28_PORT_B_address_reg, F1_ram_block1a28_PORT_A_write_enable_reg, , , , F1_ram_block1a28_clock_0, , F1_ram_block1a28_clock_enable_0, , , );
F1_ram_block1a28 = F1_ram_block1a28_PORT_A_data_out[0];


--H1L10 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[4]~359
--operation mode is normal

H1L10 = F1_address_reg_a[1] & (H1L9 & (F1_ram_block1a28) # !H1L9 & F1_ram_block1a20) # !F1_address_reg_a[1] & (H1L9);


--F1_ram_block1a11 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a11
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a11_PORT_A_data_in = D1_datain[3];
F1_ram_block1a11_PORT_A_data_in_reg = DFFE(F1_ram_block1a11_PORT_A_data_in, F1_ram_block1a11_clock_0, , , F1_ram_block1a11_clock_enable_0);
F1_ram_block1a11_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a11_PORT_A_address_reg = DFFE(F1_ram_block1a11_PORT_A_address, F1_ram_block1a11_clock_0, , , F1_ram_block1a11_clock_enable_0);
F1_ram_block1a11_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a11_PORT_B_address_reg = DFFE(F1_ram_block1a11_PORT_B_address, F1_ram_block1a11_clock_0, , , F1_ram_block1a11_clock_enable_0);
F1_ram_block1a11_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a11_PORT_A_write_enable_reg = DFFE(F1_ram_block1a11_PORT_A_write_enable, F1_ram_block1a11_clock_0, , , F1_ram_block1a11_clock_enable_0);
F1_ram_block1a11_clock_0 = C1L1;
F1_ram_block1a11_clock_enable_0 = G1L6;
F1_ram_block1a11_PORT_A_data_out = MEMORY(F1_ram_block1a11_PORT_A_data_in_reg, , F1_ram_block1a11_PORT_A_address_reg, F1_ram_block1a11_PORT_B_address_reg, F1_ram_block1a11_PORT_A_write_enable_reg, , , , F1_ram_block1a11_clock_0, , F1_ram_block1a11_clock_enable_0, , , );
F1_ram_block1a11 = F1_ram_block1a11_PORT_A_data_out[0];


--F1_ram_block1a19 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a19
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a19_PORT_A_data_in = D1_datain[3];
F1_ram_block1a19_PORT_A_data_in_reg = DFFE(F1_ram_block1a19_PORT_A_data_in, F1_ram_block1a19_clock_0, , , F1_ram_block1a19_clock_enable_0);
F1_ram_block1a19_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a19_PORT_A_address_reg = DFFE(F1_ram_block1a19_PORT_A_address, F1_ram_block1a19_clock_0, , , F1_ram_block1a19_clock_enable_0);
F1_ram_block1a19_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a19_PORT_B_address_reg = DFFE(F1_ram_block1a19_PORT_B_address, F1_ram_block1a19_clock_0, , , F1_ram_block1a19_clock_enable_0);
F1_ram_block1a19_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a19_PORT_A_write_enable_reg = DFFE(F1_ram_block1a19_PORT_A_write_enable, F1_ram_block1a19_clock_0, , , F1_ram_block1a19_clock_enable_0);
F1_ram_block1a19_clock_0 = C1L1;
F1_ram_block1a19_clock_enable_0 = G1L9;
F1_ram_block1a19_PORT_A_data_out = MEMORY(F1_ram_block1a19_PORT_A_data_in_reg, , F1_ram_block1a19_PORT_A_address_reg, F1_ram_block1a19_PORT_B_address_reg, F1_ram_block1a19_PORT_A_write_enable_reg, , , , F1_ram_block1a19_clock_0, , F1_ram_block1a19_clock_enable_0, , , );
F1_ram_block1a19 = F1_ram_block1a19_PORT_A_data_out[0];


--F1_ram_block1a3 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a3
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a3_PORT_A_data_in = D1_datain[3];
F1_ram_block1a3_PORT_A_data_in_reg = DFFE(F1_ram_block1a3_PORT_A_data_in, F1_ram_block1a3_clock_0, , , F1_ram_block1a3_clock_enable_0);
F1_ram_block1a3_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a3_PORT_A_address_reg = DFFE(F1_ram_block1a3_PORT_A_address, F1_ram_block1a3_clock_0, , , F1_ram_block1a3_clock_enable_0);
F1_ram_block1a3_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a3_PORT_B_address_reg = DFFE(F1_ram_block1a3_PORT_B_address, F1_ram_block1a3_clock_0, , , F1_ram_block1a3_clock_enable_0);
F1_ram_block1a3_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a3_PORT_A_write_enable_reg = DFFE(F1_ram_block1a3_PORT_A_write_enable, F1_ram_block1a3_clock_0, , , F1_ram_block1a3_clock_enable_0);
F1_ram_block1a3_clock_0 = C1L1;
F1_ram_block1a3_clock_enable_0 = G1L3;
F1_ram_block1a3_PORT_A_data_out = MEMORY(F1_ram_block1a3_PORT_A_data_in_reg, , F1_ram_block1a3_PORT_A_address_reg, F1_ram_block1a3_PORT_B_address_reg, F1_ram_block1a3_PORT_A_write_enable_reg, , , , F1_ram_block1a3_clock_0, , F1_ram_block1a3_clock_enable_0, , , );
F1_ram_block1a3 = F1_ram_block1a3_PORT_A_data_out[0];


--H1L7 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[3]~360
--operation mode is normal

H1L7 = F1_address_reg_a[0] & (F1_address_reg_a[1]) # !F1_address_reg_a[0] & (F1_address_reg_a[1] & F1_ram_block1a19 # !F1_address_reg_a[1] & (F1_ram_block1a3));


--F1_ram_block1a27 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a27
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a27_PORT_A_data_in = D1_datain[3];
F1_ram_block1a27_PORT_A_data_in_reg = DFFE(F1_ram_block1a27_PORT_A_data_in, F1_ram_block1a27_clock_0, , , F1_ram_block1a27_clock_enable_0);
F1_ram_block1a27_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a27_PORT_A_address_reg = DFFE(F1_ram_block1a27_PORT_A_address, F1_ram_block1a27_clock_0, , , F1_ram_block1a27_clock_enable_0);
F1_ram_block1a27_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a27_PORT_B_address_reg = DFFE(F1_ram_block1a27_PORT_B_address, F1_ram_block1a27_clock_0, , , F1_ram_block1a27_clock_enable_0);
F1_ram_block1a27_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a27_PORT_A_write_enable_reg = DFFE(F1_ram_block1a27_PORT_A_write_enable, F1_ram_block1a27_clock_0, , , F1_ram_block1a27_clock_enable_0);
F1_ram_block1a27_clock_0 = C1L1;
F1_ram_block1a27_clock_enable_0 = G1L12;
F1_ram_block1a27_PORT_A_data_out = MEMORY(F1_ram_block1a27_PORT_A_data_in_reg, , F1_ram_block1a27_PORT_A_address_reg, F1_ram_block1a27_PORT_B_address_reg, F1_ram_block1a27_PORT_A_write_enable_reg, , , , F1_ram_block1a27_clock_0, , F1_ram_block1a27_clock_enable_0, , , );
F1_ram_block1a27 = F1_ram_block1a27_PORT_A_data_out[0];


--H1L8 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[3]~361
--operation mode is normal

H1L8 = F1_address_reg_a[0] & (H1L7 & (F1_ram_block1a27) # !H1L7 & F1_ram_block1a11) # !F1_address_reg_a[0] & (H1L7);


--F1_ram_block1a18 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a18
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a18_PORT_A_data_in = D1_datain[2];
F1_ram_block1a18_PORT_A_data_in_reg = DFFE(F1_ram_block1a18_PORT_A_data_in, F1_ram_block1a18_clock_0, , , F1_ram_block1a18_clock_enable_0);
F1_ram_block1a18_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a18_PORT_A_address_reg = DFFE(F1_ram_block1a18_PORT_A_address, F1_ram_block1a18_clock_0, , , F1_ram_block1a18_clock_enable_0);
F1_ram_block1a18_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a18_PORT_B_address_reg = DFFE(F1_ram_block1a18_PORT_B_address, F1_ram_block1a18_clock_0, , , F1_ram_block1a18_clock_enable_0);
F1_ram_block1a18_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a18_PORT_A_write_enable_reg = DFFE(F1_ram_block1a18_PORT_A_write_enable, F1_ram_block1a18_clock_0, , , F1_ram_block1a18_clock_enable_0);
F1_ram_block1a18_clock_0 = C1L1;
F1_ram_block1a18_clock_enable_0 = G1L9;
F1_ram_block1a18_PORT_A_data_out = MEMORY(F1_ram_block1a18_PORT_A_data_in_reg, , F1_ram_block1a18_PORT_A_address_reg, F1_ram_block1a18_PORT_B_address_reg, F1_ram_block1a18_PORT_A_write_enable_reg, , , , F1_ram_block1a18_clock_0, , F1_ram_block1a18_clock_enable_0, , , );
F1_ram_block1a18 = F1_ram_block1a18_PORT_A_data_out[0];


--F1_ram_block1a10 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a10
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a10_PORT_A_data_in = D1_datain[2];
F1_ram_block1a10_PORT_A_data_in_reg = DFFE(F1_ram_block1a10_PORT_A_data_in, F1_ram_block1a10_clock_0, , , F1_ram_block1a10_clock_enable_0);
F1_ram_block1a10_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a10_PORT_A_address_reg = DFFE(F1_ram_block1a10_PORT_A_address, F1_ram_block1a10_clock_0, , , F1_ram_block1a10_clock_enable_0);