soundsample.map.eqn

语音采集,直接在QUARTUSII中打开调试.

F1_ram_block1a14_clock_0 = C1L1;
F1_ram_block1a14_clock_enable_0 = G1L6;
F1_ram_block1a14_PORT_A_data_out = MEMORY(F1_ram_block1a14_PORT_A_data_in_reg, , F1_ram_block1a14_PORT_A_address_reg, F1_ram_block1a14_PORT_B_address_reg, F1_ram_block1a14_PORT_A_write_enable_reg, , , , F1_ram_block1a14_clock_0, , F1_ram_block1a14_clock_enable_0, , , );
F1_ram_block1a14 = F1_ram_block1a14_PORT_A_data_out[0];


--F1_ram_block1a6 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a6
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a6_PORT_A_data_in = D1_datain[6];
F1_ram_block1a6_PORT_A_data_in_reg = DFFE(F1_ram_block1a6_PORT_A_data_in, F1_ram_block1a6_clock_0, , , F1_ram_block1a6_clock_enable_0);
F1_ram_block1a6_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a6_PORT_A_address_reg = DFFE(F1_ram_block1a6_PORT_A_address, F1_ram_block1a6_clock_0, , , F1_ram_block1a6_clock_enable_0);
F1_ram_block1a6_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a6_PORT_B_address_reg = DFFE(F1_ram_block1a6_PORT_B_address, F1_ram_block1a6_clock_0, , , F1_ram_block1a6_clock_enable_0);
F1_ram_block1a6_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a6_PORT_A_write_enable_reg = DFFE(F1_ram_block1a6_PORT_A_write_enable, F1_ram_block1a6_clock_0, , , F1_ram_block1a6_clock_enable_0);
F1_ram_block1a6_clock_0 = C1L1;
F1_ram_block1a6_clock_enable_0 = G1L3;
F1_ram_block1a6_PORT_A_data_out = MEMORY(F1_ram_block1a6_PORT_A_data_in_reg, , F1_ram_block1a6_PORT_A_address_reg, F1_ram_block1a6_PORT_B_address_reg, F1_ram_block1a6_PORT_A_write_enable_reg, , , , F1_ram_block1a6_clock_0, , F1_ram_block1a6_clock_enable_0, , , );
F1_ram_block1a6 = F1_ram_block1a6_PORT_A_data_out[0];


--H1L13 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[6]~354
--operation mode is normal

H1L13 = F1_address_reg_a[1] & (F1_address_reg_a[0]) # !F1_address_reg_a[1] & (F1_address_reg_a[0] & F1_ram_block1a14 # !F1_address_reg_a[0] & (F1_ram_block1a6));


--F1_ram_block1a30 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a30
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a30_PORT_A_data_in = D1_datain[6];
F1_ram_block1a30_PORT_A_data_in_reg = DFFE(F1_ram_block1a30_PORT_A_data_in, F1_ram_block1a30_clock_0, , , F1_ram_block1a30_clock_enable_0);
F1_ram_block1a30_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a30_PORT_A_address_reg = DFFE(F1_ram_block1a30_PORT_A_address, F1_ram_block1a30_clock_0, , , F1_ram_block1a30_clock_enable_0);
F1_ram_block1a30_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a30_PORT_B_address_reg = DFFE(F1_ram_block1a30_PORT_B_address, F1_ram_block1a30_clock_0, , , F1_ram_block1a30_clock_enable_0);
F1_ram_block1a30_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a30_PORT_A_write_enable_reg = DFFE(F1_ram_block1a30_PORT_A_write_enable, F1_ram_block1a30_clock_0, , , F1_ram_block1a30_clock_enable_0);
F1_ram_block1a30_clock_0 = C1L1;
F1_ram_block1a30_clock_enable_0 = G1L12;
F1_ram_block1a30_PORT_A_data_out = MEMORY(F1_ram_block1a30_PORT_A_data_in_reg, , F1_ram_block1a30_PORT_A_address_reg, F1_ram_block1a30_PORT_B_address_reg, F1_ram_block1a30_PORT_A_write_enable_reg, , , , F1_ram_block1a30_clock_0, , F1_ram_block1a30_clock_enable_0, , , );
F1_ram_block1a30 = F1_ram_block1a30_PORT_A_data_out[0];


--H1L14 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[6]~355
--operation mode is normal

H1L14 = F1_address_reg_a[1] & (H1L13 & (F1_ram_block1a30) # !H1L13 & F1_ram_block1a22) # !F1_address_reg_a[1] & (H1L13);


--F1_ram_block1a13 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a13
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a13_PORT_A_data_in = D1_datain[5];
F1_ram_block1a13_PORT_A_data_in_reg = DFFE(F1_ram_block1a13_PORT_A_data_in, F1_ram_block1a13_clock_0, , , F1_ram_block1a13_clock_enable_0);
F1_ram_block1a13_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a13_PORT_A_address_reg = DFFE(F1_ram_block1a13_PORT_A_address, F1_ram_block1a13_clock_0, , , F1_ram_block1a13_clock_enable_0);
F1_ram_block1a13_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a13_PORT_B_address_reg = DFFE(F1_ram_block1a13_PORT_B_address, F1_ram_block1a13_clock_0, , , F1_ram_block1a13_clock_enable_0);
F1_ram_block1a13_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a13_PORT_A_write_enable_reg = DFFE(F1_ram_block1a13_PORT_A_write_enable, F1_ram_block1a13_clock_0, , , F1_ram_block1a13_clock_enable_0);
F1_ram_block1a13_clock_0 = C1L1;
F1_ram_block1a13_clock_enable_0 = G1L6;
F1_ram_block1a13_PORT_A_data_out = MEMORY(F1_ram_block1a13_PORT_A_data_in_reg, , F1_ram_block1a13_PORT_A_address_reg, F1_ram_block1a13_PORT_B_address_reg, F1_ram_block1a13_PORT_A_write_enable_reg, , , , F1_ram_block1a13_clock_0, , F1_ram_block1a13_clock_enable_0, , , );
F1_ram_block1a13 = F1_ram_block1a13_PORT_A_data_out[0];


--F1_ram_block1a21 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a21
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a21_PORT_A_data_in = D1_datain[5];
F1_ram_block1a21_PORT_A_data_in_reg = DFFE(F1_ram_block1a21_PORT_A_data_in, F1_ram_block1a21_clock_0, , , F1_ram_block1a21_clock_enable_0);
F1_ram_block1a21_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a21_PORT_A_address_reg = DFFE(F1_ram_block1a21_PORT_A_address, F1_ram_block1a21_clock_0, , , F1_ram_block1a21_clock_enable_0);
F1_ram_block1a21_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a21_PORT_B_address_reg = DFFE(F1_ram_block1a21_PORT_B_address, F1_ram_block1a21_clock_0, , , F1_ram_block1a21_clock_enable_0);
F1_ram_block1a21_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a21_PORT_A_write_enable_reg = DFFE(F1_ram_block1a21_PORT_A_write_enable, F1_ram_block1a21_clock_0, , , F1_ram_block1a21_clock_enable_0);
F1_ram_block1a21_clock_0 = C1L1;
F1_ram_block1a21_clock_enable_0 = G1L9;
F1_ram_block1a21_PORT_A_data_out = MEMORY(F1_ram_block1a21_PORT_A_data_in_reg, , F1_ram_block1a21_PORT_A_address_reg, F1_ram_block1a21_PORT_B_address_reg, F1_ram_block1a21_PORT_A_write_enable_reg, , , , F1_ram_block1a21_clock_0, , F1_ram_block1a21_clock_enable_0, , , );
F1_ram_block1a21 = F1_ram_block1a21_PORT_A_data_out[0];


--F1_ram_block1a5 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a5
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a5_PORT_A_data_in = D1_datain[5];
F1_ram_block1a5_PORT_A_data_in_reg = DFFE(F1_ram_block1a5_PORT_A_data_in, F1_ram_block1a5_clock_0, , , F1_ram_block1a5_clock_enable_0);
F1_ram_block1a5_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a5_PORT_A_address_reg = DFFE(F1_ram_block1a5_PORT_A_address, F1_ram_block1a5_clock_0, , , F1_ram_block1a5_clock_enable_0);
F1_ram_block1a5_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a5_PORT_B_address_reg = DFFE(F1_ram_block1a5_PORT_B_address, F1_ram_block1a5_clock_0, , , F1_ram_block1a5_clock_enable_0);
F1_ram_block1a5_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a5_PORT_A_write_enable_reg = DFFE(F1_ram_block1a5_PORT_A_write_enable, F1_ram_block1a5_clock_0, , , F1_ram_block1a5_clock_enable_0);
F1_ram_block1a5_clock_0 = C1L1;
F1_ram_block1a5_clock_enable_0 = G1L3;
F1_ram_block1a5_PORT_A_data_out = MEMORY(F1_ram_block1a5_PORT_A_data_in_reg, , F1_ram_block1a5_PORT_A_address_reg, F1_ram_block1a5_PORT_B_address_reg, F1_ram_block1a5_PORT_A_write_enable_reg, , , , F1_ram_block1a5_clock_0, , F1_ram_block1a5_clock_enable_0, , , );
F1_ram_block1a5 = F1_ram_block1a5_PORT_A_data_out[0];


--H1L11 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[5]~356
--operation mode is normal

H1L11 = F1_address_reg_a[0] & (F1_address_reg_a[1]) # !F1_address_reg_a[0] & (F1_address_reg_a[1] & F1_ram_block1a21 # !F1_address_reg_a[1] & (F1_ram_block1a5));


--F1_ram_block1a29 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a29
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a29_PORT_A_data_in = D1_datain[5];
F1_ram_block1a29_PORT_A_data_in_reg = DFFE(F1_ram_block1a29_PORT_A_data_in, F1_ram_block1a29_clock_0, , , F1_ram_block1a29_clock_enable_0);
F1_ram_block1a29_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a29_PORT_A_address_reg = DFFE(F1_ram_block1a29_PORT_A_address, F1_ram_block1a29_clock_0, , , F1_ram_block1a29_clock_enable_0);
F1_ram_block1a29_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a29_PORT_B_address_reg = DFFE(F1_ram_block1a29_PORT_B_address, F1_ram_block1a29_clock_0, , , F1_ram_block1a29_clock_enable_0);
F1_ram_block1a29_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a29_PORT_A_write_enable_reg = DFFE(F1_ram_block1a29_PORT_A_write_enable, F1_ram_block1a29_clock_0, , , F1_ram_block1a29_clock_enable_0);
F1_ram_block1a29_clock_0 = C1L1;
F1_ram_block1a29_clock_enable_0 = G1L12;
F1_ram_block1a29_PORT_A_data_out = MEMORY(F1_ram_block1a29_PORT_A_data_in_reg, , F1_ram_block1a29_PORT_A_address_reg, F1_ram_block1a29_PORT_B_address_reg, F1_ram_block1a29_PORT_A_write_enable_reg, , , , F1_ram_block1a29_clock_0, , F1_ram_block1a29_clock_enable_0, , , );
F1_ram_block1a29 = F1_ram_block1a29_PORT_A_data_out[0];


--H1L12 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[5]~357
--operation mode is normal

H1L12 = F1_address_reg_a[0] & (H1L11 & (F1_ram_block1a29) # !H1L11 & F1_ram_block1a13) # !F1_address_reg_a[0] & (H1L11);


--F1_ram_block1a20 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a20
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a20_PORT_A_data_in = D1_datain[4];
F1_ram_block1a20_PORT_A_data_in_reg = DFFE(F1_ram_block1a20_PORT_A_data_in, F1_ram_block1a20_clock_0, , , F1_ram_block1a20_clock_enable_0);
F1_ram_block1a20_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a20_PORT_A_address_reg = DFFE(F1_ram_block1a20_PORT_A_address, F1_ram_block1a20_clock_0, , , F1_ram_block1a20_clock_enable_0);
F1_ram_block1a20_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a20_PORT_B_address_reg = DFFE(F1_ram_block1a20_PORT_B_address, F1_ram_block1a20_clock_0, , , F1_ram_block1a20_clock_enable_0);
F1_ram_block1a20_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a20_PORT_A_write_enable_reg = DFFE(F1_ram_block1a20_PORT_A_write_enable, F1_ram_block1a20_clock_0, , , F1_ram_block1a20_clock_enable_0);
F1_ram_block1a20_clock_0 = C1L1;
F1_ram_block1a20_clock_enable_0 = G1L9;
F1_ram_block1a20_PORT_A_data_out = MEMORY(F1_ram_block1a20_PORT_A_data_in_reg, , F1_ram_block1a20_PORT_A_address_reg, F1_ram_block1a20_PORT_B_address_reg, F1_ram_block1a20_PORT_A_write_enable_reg, , , , F1_ram_block1a20_clock_0, , F1_ram_block1a20_clock_enable_0, , , );
F1_ram_block1a20 = F1_ram_block1a20_PORT_A_data_out[0];


--F1_ram_block1a12 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a12
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a12_PORT_A_data_in = D1_datain[4];
F1_ram_block1a12_PORT_A_data_in_reg = DFFE(F1_ram_block1a12_PORT_A_data_in, F1_ram_block1a12_clock_0, , , F1_ram_block1a12_clock_enable_0);
F1_ram_block1a12_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a12_PORT_A_address_reg = DFFE(F1_ram_block1a12_PORT_A_address, F1_ram_block1a12_clock_0, , , F1_ram_block1a12_clock_enable_0);
F1_ram_block1a12_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a12_PORT_B_address_reg = DFFE(F1_ram_block1a12_PORT_B_address, F1_ram_block1a12_clock_0, , , F1_ram_block1a12_clock_enable_0);