soundsample.map.eqn

语音采集,直接在QUARTUSII中打开调试.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--D1_present_state.read is ad0809:inst2|present_state.read
--operation mode is normal

D1_present_state.read_lut_out = !INT & (D1_present_state.swait);
D1_present_state.read = DFFEAS(D1_present_state.read_lut_out, CLK, CLR, , , , , , );


--D1_present_state.slock is ad0809:inst2|present_state.slock
--operation mode is normal

D1_present_state.slock_lut_out = D1_present_state.read;
D1_present_state.slock = DFFEAS(D1_present_state.slock_lut_out, CLK, CLR, , , , , , );


--D1L15 is ad0809:inst2|RD~0
--operation mode is normal

D1L15 = D1_present_state.read # D1_present_state.slock;


--D1_present_state.write is ad0809:inst2|present_state.write
--operation mode is normal

D1_present_state.write_lut_out = !D1_present_state.idle;
D1_present_state.write = DFFEAS(D1_present_state.write_lut_out, CLK, CLR, , , , , , );


--F1_ram_block1a15 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a15
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a15_PORT_A_data_in = D1_datain[7];
F1_ram_block1a15_PORT_A_data_in_reg = DFFE(F1_ram_block1a15_PORT_A_data_in, F1_ram_block1a15_clock_0, , , F1_ram_block1a15_clock_enable_0);
F1_ram_block1a15_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a15_PORT_A_address_reg = DFFE(F1_ram_block1a15_PORT_A_address, F1_ram_block1a15_clock_0, , , F1_ram_block1a15_clock_enable_0);
F1_ram_block1a15_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a15_PORT_B_address_reg = DFFE(F1_ram_block1a15_PORT_B_address, F1_ram_block1a15_clock_0, , , F1_ram_block1a15_clock_enable_0);
F1_ram_block1a15_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a15_PORT_A_write_enable_reg = DFFE(F1_ram_block1a15_PORT_A_write_enable, F1_ram_block1a15_clock_0, , , F1_ram_block1a15_clock_enable_0);
F1_ram_block1a15_clock_0 = C1L1;
F1_ram_block1a15_clock_enable_0 = G1L6;
F1_ram_block1a15_PORT_A_data_out = MEMORY(F1_ram_block1a15_PORT_A_data_in_reg, , F1_ram_block1a15_PORT_A_address_reg, F1_ram_block1a15_PORT_B_address_reg, F1_ram_block1a15_PORT_A_write_enable_reg, , , , F1_ram_block1a15_clock_0, , F1_ram_block1a15_clock_enable_0, , , );
F1_ram_block1a15 = F1_ram_block1a15_PORT_A_data_out[0];


--F1_address_reg_a[0] is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|address_reg_a[0]
--operation mode is normal

F1_address_reg_a[0]_lut_out = C1_CQI[12];
F1_address_reg_a[0] = DFFEAS(F1_address_reg_a[0]_lut_out, C1L1, VCC, , , , , , );


--F1_ram_block1a23 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a23
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a23_PORT_A_data_in = D1_datain[7];
F1_ram_block1a23_PORT_A_data_in_reg = DFFE(F1_ram_block1a23_PORT_A_data_in, F1_ram_block1a23_clock_0, , , F1_ram_block1a23_clock_enable_0);
F1_ram_block1a23_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a23_PORT_A_address_reg = DFFE(F1_ram_block1a23_PORT_A_address, F1_ram_block1a23_clock_0, , , F1_ram_block1a23_clock_enable_0);
F1_ram_block1a23_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a23_PORT_B_address_reg = DFFE(F1_ram_block1a23_PORT_B_address, F1_ram_block1a23_clock_0, , , F1_ram_block1a23_clock_enable_0);
F1_ram_block1a23_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a23_PORT_A_write_enable_reg = DFFE(F1_ram_block1a23_PORT_A_write_enable, F1_ram_block1a23_clock_0, , , F1_ram_block1a23_clock_enable_0);
F1_ram_block1a23_clock_0 = C1L1;
F1_ram_block1a23_clock_enable_0 = G1L9;
F1_ram_block1a23_PORT_A_data_out = MEMORY(F1_ram_block1a23_PORT_A_data_in_reg, , F1_ram_block1a23_PORT_A_address_reg, F1_ram_block1a23_PORT_B_address_reg, F1_ram_block1a23_PORT_A_write_enable_reg, , , , F1_ram_block1a23_clock_0, , F1_ram_block1a23_clock_enable_0, , , );
F1_ram_block1a23 = F1_ram_block1a23_PORT_A_data_out[0];


--F1_address_reg_a[1] is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|address_reg_a[1]
--operation mode is normal

F1_address_reg_a[1]_lut_out = C1_CQI[13];
F1_address_reg_a[1] = DFFEAS(F1_address_reg_a[1]_lut_out, C1L1, VCC, , , , , , );


--F1_ram_block1a7 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a7
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a7_PORT_A_data_in = D1_datain[7];
F1_ram_block1a7_PORT_A_data_in_reg = DFFE(F1_ram_block1a7_PORT_A_data_in, F1_ram_block1a7_clock_0, , , F1_ram_block1a7_clock_enable_0);
F1_ram_block1a7_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a7_PORT_A_address_reg = DFFE(F1_ram_block1a7_PORT_A_address, F1_ram_block1a7_clock_0, , , F1_ram_block1a7_clock_enable_0);
F1_ram_block1a7_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a7_PORT_B_address_reg = DFFE(F1_ram_block1a7_PORT_B_address, F1_ram_block1a7_clock_0, , , F1_ram_block1a7_clock_enable_0);
F1_ram_block1a7_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a7_PORT_A_write_enable_reg = DFFE(F1_ram_block1a7_PORT_A_write_enable, F1_ram_block1a7_clock_0, , , F1_ram_block1a7_clock_enable_0);
F1_ram_block1a7_clock_0 = C1L1;
F1_ram_block1a7_clock_enable_0 = G1L3;
F1_ram_block1a7_PORT_A_data_out = MEMORY(F1_ram_block1a7_PORT_A_data_in_reg, , F1_ram_block1a7_PORT_A_address_reg, F1_ram_block1a7_PORT_B_address_reg, F1_ram_block1a7_PORT_A_write_enable_reg, , , , F1_ram_block1a7_clock_0, , F1_ram_block1a7_clock_enable_0, , , );
F1_ram_block1a7 = F1_ram_block1a7_PORT_A_data_out[0];


--H1L15 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[7]~352
--operation mode is normal

H1L15 = F1_address_reg_a[0] & (F1_address_reg_a[1]) # !F1_address_reg_a[0] & (F1_address_reg_a[1] & F1_ram_block1a23 # !F1_address_reg_a[1] & (F1_ram_block1a7));


--F1_ram_block1a31 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a31
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a31_PORT_A_data_in = D1_datain[7];
F1_ram_block1a31_PORT_A_data_in_reg = DFFE(F1_ram_block1a31_PORT_A_data_in, F1_ram_block1a31_clock_0, , , F1_ram_block1a31_clock_enable_0);
F1_ram_block1a31_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a31_PORT_A_address_reg = DFFE(F1_ram_block1a31_PORT_A_address, F1_ram_block1a31_clock_0, , , F1_ram_block1a31_clock_enable_0);
F1_ram_block1a31_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a31_PORT_B_address_reg = DFFE(F1_ram_block1a31_PORT_B_address, F1_ram_block1a31_clock_0, , , F1_ram_block1a31_clock_enable_0);
F1_ram_block1a31_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a31_PORT_A_write_enable_reg = DFFE(F1_ram_block1a31_PORT_A_write_enable, F1_ram_block1a31_clock_0, , , F1_ram_block1a31_clock_enable_0);
F1_ram_block1a31_clock_0 = C1L1;
F1_ram_block1a31_clock_enable_0 = G1L12;
F1_ram_block1a31_PORT_A_data_out = MEMORY(F1_ram_block1a31_PORT_A_data_in_reg, , F1_ram_block1a31_PORT_A_address_reg, F1_ram_block1a31_PORT_B_address_reg, F1_ram_block1a31_PORT_A_write_enable_reg, , , , F1_ram_block1a31_clock_0, , F1_ram_block1a31_clock_enable_0, , , );
F1_ram_block1a31 = F1_ram_block1a31_PORT_A_data_out[0];


--H1L16 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[7]~353
--operation mode is normal

H1L16 = F1_address_reg_a[0] & (H1L15 & (F1_ram_block1a31) # !H1L15 & F1_ram_block1a15) # !F1_address_reg_a[0] & (H1L15);


--F1_ram_block1a22 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a22
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a22_PORT_A_data_in = D1_datain[6];
F1_ram_block1a22_PORT_A_data_in_reg = DFFE(F1_ram_block1a22_PORT_A_data_in, F1_ram_block1a22_clock_0, , , F1_ram_block1a22_clock_enable_0);
F1_ram_block1a22_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a22_PORT_A_address_reg = DFFE(F1_ram_block1a22_PORT_A_address, F1_ram_block1a22_clock_0, , , F1_ram_block1a22_clock_enable_0);
F1_ram_block1a22_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a22_PORT_B_address_reg = DFFE(F1_ram_block1a22_PORT_B_address, F1_ram_block1a22_clock_0, , , F1_ram_block1a22_clock_enable_0);
F1_ram_block1a22_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a22_PORT_A_write_enable_reg = DFFE(F1_ram_block1a22_PORT_A_write_enable, F1_ram_block1a22_clock_0, , , F1_ram_block1a22_clock_enable_0);
F1_ram_block1a22_clock_0 = C1L1;
F1_ram_block1a22_clock_enable_0 = G1L9;
F1_ram_block1a22_PORT_A_data_out = MEMORY(F1_ram_block1a22_PORT_A_data_in_reg, , F1_ram_block1a22_PORT_A_address_reg, F1_ram_block1a22_PORT_B_address_reg, F1_ram_block1a22_PORT_A_write_enable_reg, , , , F1_ram_block1a22_clock_0, , F1_ram_block1a22_clock_enable_0, , , );
F1_ram_block1a22 = F1_ram_block1a22_PORT_A_data_out[0];


--F1_ram_block1a14 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a14
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a14_PORT_A_data_in = D1_datain[6];
F1_ram_block1a14_PORT_A_data_in_reg = DFFE(F1_ram_block1a14_PORT_A_data_in, F1_ram_block1a14_clock_0, , , F1_ram_block1a14_clock_enable_0);
F1_ram_block1a14_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a14_PORT_A_address_reg = DFFE(F1_ram_block1a14_PORT_A_address, F1_ram_block1a14_clock_0, , , F1_ram_block1a14_clock_enable_0);
F1_ram_block1a14_PORT_B_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a14_PORT_B_address_reg = DFFE(F1_ram_block1a14_PORT_B_address, F1_ram_block1a14_clock_0, , , F1_ram_block1a14_clock_enable_0);
F1_ram_block1a14_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a14_PORT_A_write_enable_reg = DFFE(F1_ram_block1a14_PORT_A_write_enable, F1_ram_block1a14_clock_0, , , F1_ram_block1a14_clock_enable_0);