songer.tan.rpt
来自「乐曲硬件演奏电路设计的全部VHDL代码」· RPT 代码 · 共 326 行 · 第 1/5 页
RPT
326 行
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK12MHZ ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK12MHZ' ;
+-----------------------------------------+-----------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 60.98 MHz ( period = 16.400 ns ) ; count12MHz[2] ; count12MHz[0] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.300 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[9] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[7] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[3] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[17] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[11] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[10] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[16] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[2] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.11 MHz ( period = 16.100 ns ) ; count12MHz[2] ; count12MHz[1] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 15.000 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; count12MHz[2] ; count12MHz[8] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.900 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; count12MHz[2] ; count12MHz[6] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.900 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; count12MHz[2] ; count12MHz[5] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.900 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; count12MHz[2] ; count12MHz[4] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.900 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; count12MHz[2] ; count12MHz[12] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.900 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; count12MHz[4] ; count12MHz[0] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.900 ns ;
; N/A ; 62.89 MHz ( period = 15.900 ns ) ; count12MHz[1] ; count12MHz[0] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.800 ns ;
; N/A ; 63.29 MHz ( period = 15.800 ns ) ; count12MHz[5] ; count12MHz[0] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.700 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[9] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[7] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[3] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[17] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[11] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[10] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[16] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[2] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; count12MHz[4] ; count12MHz[1] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.600 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[9] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[4] ; count12MHz[8] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[7] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[4] ; count12MHz[6] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[4] ; count12MHz[5] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[4] ; count12MHz[4] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[3] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[17] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[11] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[10] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[16] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[4] ; count12MHz[12] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[2] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; count12MHz[1] ; count12MHz[1] ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.500 ns ;
; N/A ; 64.52 MHz ( period = 15.500 ns ) ; count12MHz[2] ; CLK8HZ ; CLK12MHZ ; CLK12MHZ ; None ; None ; 14.400 ns ;
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