songer.tan.qmsg

乐曲硬件演奏电路设计的全部VHDL代码

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK12MHZ 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"CLK12MHZ\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~reg_ra0 ToneTaba:u2\|HIGH CLK12MHZ 2.8 ns " "Info: Found hold time violation between source  pin or register \"NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[3\]~reg_ra0\" and destination pin or register \"ToneTaba:u2\|HIGH\" for clock \"CLK12MHZ\" (Hold time is 2.8 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "12.800 ns + Largest " "Info: + Largest clock skew is 12.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHZ destination 17.900 ns + Longest register " "Info: + Longest clock path from clock \"CLK12MHZ\" to destination register is 17.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns CLK12MHZ 1 CLK PIN_79 26 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_79; Fanout = 26; CLK Node = 'CLK12MHZ'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK12MHZ } "NODE_NAME" } } { "Songer.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/Songer.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns CLK8HZ 2 REG LC6_A35 48 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC6_A35; Fanout = 48; REG Node = 'CLK8HZ'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.900 ns" { CLK12MHZ CLK8HZ } "NODE_NAME" } } { "Songer.vhd" "" { Text "F:/课程/电子设计自动化/2007年秋季/乐曲硬件演奏电路设计QuartusVHDL/data/Songer.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(0.400 ns) 5.500 ns NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[1\]~reg_ra7 3 MEM EC1_A 1 " "Info: 3: + IC(2.200 ns) + CELL(0.400 ns) = 5.500 ns; Loc. = EC1_A; Fanout = 1; MEM Node = 'NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[1\]~reg_ra7'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { CLK8HZ NoteTabs:u1|music:u1|lpm_rom:lpm_rom_component|altrom:srom|q[1]~reg_ra7 } "NODE_NAME" } } { "altrom.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 9.900 ns NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[1\]~mem_cell_ra0 4 MEM EC1_A 1 " "Info: 4: + IC(0.000 ns) + CELL(4.400 ns) = 9.900 ns; Loc. = EC1_A; Fanout = 1; MEM Node = 'NoteTabs:u1\|music:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[1\]~mem_cell_ra0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { NoteTabs: