frequency_divider.v

来自「用VERILOG HDL实现的任意 频率分频器源代码」· Verilog 代码 · 共 44 行

//--------------------------------------//
//module name: Frequency_divider--------//
//file   name: Frequency_divider.v------//
//module function:
//            Frequency_divider---------//
//Coder      : h0nly--------------------//
//Time       : 2008-08-13th 11:00pm-----//
//--------------------------------------//
module Frequency_divider(
						 reset,
						 en,
						 sel,
						 clk_in,
						 clk_out,
						 count 
						);
//
//output ports----------------------------
output [3:0] count;
output       clk_out;
//input ports----------------------------
input        reset;
input        en;
input        clk_in;
input		 sel;
//
wire         b, c;
//code starts here------------------------
Half_sel Half_sel_1(.sel(sel),
					.a(clk_in),
					.b(b),
					.c(c)
					);
Freq_div_2  Freq_div_2_1(.clk_in(clk_out), 
                  		 .clk_out(b)
                  		 );
Counter_N   Counter_N_1(.reset(reset),
				 .en(en),
				 .clk_in(c),
				 //-------
				 .clk_out(clk_out),
				 .count(count)
				 );
endmodule