frequency_divider.hif

用VERILOG HDL实现的任意 频率分频器源代码

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1588
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
Half_sel
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Half_sel.v
1218771550
7
# storage
db|Frequency_divider.(0).cnf
db|Frequency_divider.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
Counter_N
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Counter_N.v
1218778260
7
# storage
db|Frequency_divider.(1).cnf
db|Frequency_divider.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
N
7
PARAMETER_DEC
DEF
}
# end
# entity
Freq_div_2
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
Freq_div_2.v
1218773466
7
# storage
db|Frequency_divider.(3).cnf
db|Frequency_divider.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# end
# entity
F_Div_20
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
F_Div_20.v
1218957408
7
# storage
db|Frequency_divider.(2).cnf
db|Frequency_divider.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# complete