frequency_divider.hier_info

用VERILOG HDL实现的任意 频率分频器源代码

|F_Div_20
Fout <= Fout~reg0.DB_MAX_OUTPUT_PORT_TYPE
Fin => j[6].CLK
Fin => j[5].CLK
Fin => j[4].CLK
Fin => j[3].CLK
Fin => j[2].CLK
Fin => j[1].CLK
Fin => j[0].CLK
Fin => Fout~reg0.CLK
Fin => j[7].CLK
Reset_N => j~8.OUTPUTSELECT
Reset_N => j~9.OUTPUTSELECT
Reset_N => j~10.OUTPUTSELECT
Reset_N => j~11.OUTPUTSELECT
Reset_N => j~12.OUTPUTSELECT
Reset_N => j~13.OUTPUTSELECT
Reset_N => j~14.OUTPUTSELECT
Reset_N => j~15.OUTPUTSELECT
Reset_N => Fout~1.OUTPUTSELECT