frequency_divider.tan.qmsg

用VERILOG HDL实现的任意 频率分频器源代码

{ "Info" "ITDB_TH_RESULT" "Fout~reg0 Reset_N Fin -3.093 ns register " "Info: th for register \"Fout~reg0\" (data pin = \"Reset_N\", clock pin = \"Fin\") is -3.093 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin destination 2.099 ns + Longest register " "Info: + Longest clock path from clock \"Fin\" to destination register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Fin 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Fin } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns Fout~reg0 2 REG LC_X1_Y2_N3 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X1_Y2_N3; Fanout = 2; REG Node = 'Fout~reg0'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "0.969 ns" { Fin Fout~reg0 } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin Fout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 Fout~reg0 } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.204 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.204 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Reset_N 1 PIN PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 2; PIN Node = 'Reset_N'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Reset_N } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.506 ns) + CELL(0.568 ns) 5.204 ns Fout~reg0 2 REG LC_X1_Y2_N3 2 " "Info: 2: + IC(3.506 ns) + CELL(0.568 ns) = 5.204 ns; Loc. = LC_X1_Y2_N3; Fanout = 2; REG Node = 'Fout~reg0'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "4.074 ns" { Reset_N Fout~reg0 } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.698 ns 32.63 % " "Info: Total cell delay = 1.698 ns ( 32.63 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.506 ns 67.37 % " "Info: Total interconnect delay = 3.506 ns ( 67.37 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "5.204 ns" { Reset_N Fout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.204 ns" { Reset_N Reset_N~out0 Fout~reg0 } { 0.000ns 0.000ns 3.506ns } { 0.000ns 1.130ns 0.568ns } } }  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin Fout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 Fout~reg0 } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "5.204 ns" { Reset_N Fout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.204 ns" { Reset_N Reset_N~out0 Fout~reg0 } { 0.000ns 0.000ns 3.506ns } { 0.000ns 1.130ns 0.568ns } } }  } 0}
{ "Warning" "WTAN_INVALID_ASSIGNMENTS_FOUND" "" "Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 17 15:20:58 2008 " "Info: Processing ended: Sun Aug 17 15:20:58 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}