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📄 frequency_divider.tan.qmsg

📁 用VERILOG HDL实现的任意 频率分频器源代码
💻 QMSG
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{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "clk_in " "Warning: Clock Setting \"clk_in\" is unassigned" {  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Fin register j\[7\] register j\[3\] 303.95 MHz 3.29 ns Internal " "Info: Clock \"Fin\" has Internal fmax of 303.95 MHz between source register \"j\[7\]\" and destination register \"j\[3\]\" (period= 3.29 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.088 ns + Longest register register " "Info: + Longest register to register delay is 3.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns j\[7\] 1 REG LC_X2_Y2_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y2_N7; Fanout = 2; REG Node = 'j\[7\]'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { j[7] } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.454 ns) 1.027 ns reduce_nor~41 2 COMB LC_X1_Y2_N2 2 " "Info: 2: + IC(0.573 ns) + CELL(0.454 ns) = 1.027 ns; Loc. = LC_X1_Y2_N2; Fanout = 2; COMB Node = 'reduce_nor~41'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "1.027 ns" { j[7] reduce_nor~41 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.511 ns) + CELL(0.340 ns) 1.878 ns j\[6\]~213 3 COMB LC_X2_Y2_N8 8 " "Info: 3: + IC(0.511 ns) + CELL(0.340 ns) = 1.878 ns; Loc. = LC_X2_Y2_N8; Fanout = 8; COMB Node = 'j\[6\]~213'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "0.851 ns" { reduce_nor~41 j[6]~213 } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.856 ns) 3.088 ns j\[3\] 4 REG LC_X2_Y2_N3 4 " "Info: 4: + IC(0.354 ns) + CELL(0.856 ns) = 3.088 ns; Loc. = LC_X2_Y2_N3; Fanout = 4; REG Node = 'j\[3\]'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "1.210 ns" { j[6]~213 j[3] } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns 53.43 % " "Info: Total cell delay = 1.650 ns ( 53.43 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.438 ns 46.57 % " "Info: Total interconnect delay = 1.438 ns ( 46.57 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "3.088 ns" { j[7] reduce_nor~41 j[6]~213 j[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.088 ns" { j[7] reduce_nor~41 j[6]~213 j[3] } { 0.000ns 0.573ns 0.511ns 0.354ns } { 0.000ns 0.454ns 0.340ns 0.856ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin destination 2.099 ns + Shortest register " "Info: + Shortest clock path from clock \"Fin\" to destination register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Fin 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Fin } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns j\[3\] 2 REG LC_X2_Y2_N3 4 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N3; Fanout = 4; REG Node = 'j\[3\]'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "0.969 ns" { Fin j[3] } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin j[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 j[3] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin source 2.099 ns - Longest register " "Info: - Longest clock path from clock \"Fin\" to source register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Fin 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Fin } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns j\[7\] 2 REG LC_X2_Y2_N7 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N7; Fanout = 2; REG Node = 'j\[7\]'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "0.969 ns" { Fin j[7] } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin j[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 j[7] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin j[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 j[3] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin j[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 j[7] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "3.088 ns" { j[7] reduce_nor~41 j[6]~213 j[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.088 ns" { j[7] reduce_nor~41 j[6]~213 j[3] } { 0.000ns 0.573ns 0.511ns 0.354ns } { 0.000ns 0.454ns 0.340ns 0.856ns } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin j[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 j[3] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin j[7] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 j[7] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "j\[1\] Reset_N Fin 4.160 ns register " "Info: tsu for register \"j\[1\]\" (data pin = \"Reset_N\", clock pin = \"Fin\") is 4.160 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.230 ns + Longest pin register " "Info: + Longest pin to register delay is 6.230 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Reset_N 1 PIN PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 2; PIN Node = 'Reset_N'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Reset_N } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.802 ns) + CELL(0.088 ns) 5.020 ns j\[6\]~213 2 COMB LC_X2_Y2_N8 8 " "Info: 2: + IC(3.802 ns) + CELL(0.088 ns) = 5.020 ns; Loc. = LC_X2_Y2_N8; Fanout = 8; COMB Node = 'j\[6\]~213'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "3.890 ns" { Reset_N j[6]~213 } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.856 ns) 6.230 ns j\[1\] 3 REG LC_X2_Y2_N1 4 " "Info: 3: + IC(0.354 ns) + CELL(0.856 ns) = 6.230 ns; Loc. = LC_X2_Y2_N1; Fanout = 4; REG Node = 'j\[1\]'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "1.210 ns" { j[6]~213 j[1] } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.074 ns 33.29 % " "Info: Total cell delay = 2.074 ns ( 33.29 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.156 ns 66.71 % " "Info: Total interconnect delay = 4.156 ns ( 66.71 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "6.230 ns" { Reset_N j[6]~213 j[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.230 ns" { Reset_N Reset_N~out0 j[6]~213 j[1] } { 0.000ns 0.000ns 3.802ns 0.354ns } { 0.000ns 1.130ns 0.088ns 0.856ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin destination 2.099 ns - Shortest register " "Info: - Shortest clock path from clock \"Fin\" to destination register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Fin 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Fin } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns j\[1\] 2 REG LC_X2_Y2_N1 4 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N1; Fanout = 4; REG Node = 'j\[1\]'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "0.969 ns" { Fin j[1] } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin j[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 j[1] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "6.230 ns" { Reset_N j[6]~213 j[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.230 ns" { Reset_N Reset_N~out0 j[6]~213 j[1] } { 0.000ns 0.000ns 3.802ns 0.354ns } { 0.000ns 1.130ns 0.088ns 0.856ns } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin j[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 j[1] } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Fin Fout Fout~reg0 4.782 ns register " "Info: tco from clock \"Fin\" to destination pin \"Fout\" through register \"Fout~reg0\" is 4.782 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Fin source 2.099 ns + Longest register " "Info: + Longest clock path from clock \"Fin\" to source register is 2.099 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns Fin 1 CLK PIN_10 9 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Fin } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.422 ns) + CELL(0.547 ns) 2.099 ns Fout~reg0 2 REG LC_X1_Y2_N3 2 " "Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X1_Y2_N3; Fanout = 2; REG Node = 'Fout~reg0'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "0.969 ns" { Fin Fout~reg0 } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 79.90 % " "Info: Total cell delay = 1.677 ns ( 79.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.422 ns 20.10 % " "Info: Total interconnect delay = 0.422 ns ( 20.10 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin Fout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 Fout~reg0 } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.510 ns + Longest register pin " "Info: + Longest register to pin delay is 2.510 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Fout~reg0 1 REG LC_X1_Y2_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N3; Fanout = 2; REG Node = 'Fout~reg0'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Fout~reg0 } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.876 ns) + CELL(1.634 ns) 2.510 ns Fout 2 PIN PIN_22 0 " "Info: 2: + IC(0.876 ns) + CELL(1.634 ns) = 2.510 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'Fout'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.510 ns" { Fout~reg0 Fout } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.634 ns 65.10 % " "Info: Total cell delay = 1.634 ns ( 65.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.876 ns 34.90 % " "Info: Total interconnect delay = 0.876 ns ( 34.90 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.510 ns" { Fout~reg0 Fout } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.510 ns" { Fout~reg0 Fout } { 0.000ns 0.876ns } { 0.000ns 1.634ns } } }  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.099 ns" { Fin Fout~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.099 ns" { Fin Fin~out0 Fout~reg0 } { 0.000ns 0.000ns 0.422ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.510 ns" { Fout~reg0 Fout } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.510 ns" { Fout~reg0 Fout } { 0.000ns 0.876ns } { 0.000ns 1.634ns } } }  } 0}
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