frequency_divider.map.qmsg

用VERILOG HDL实现的任意 频率分频器源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 17 15:20:52 2008 " "Info: Processing started: Sun Aug 17 15:20:52 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Frequency_divider -c Frequency_divider " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Frequency_divider -c Frequency_divider" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Frequency_divider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Frequency_divider.v" { { "Info" "ISGN_ENTITY_NAME" "1 Frequency_divider " "Info: Found entity 1: Frequency_divider" {  } { { "Frequency_divider.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/Frequency_divider.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Half_sel.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Half_sel.v" { { "Info" "ISGN_ENTITY_NAME" "1 Half_sel " "Info: Found entity 1: Half_sel" {  } { { "Half_sel.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/Half_sel.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Freq_div_2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Freq_div_2.v" { { "Info" "ISGN_ENTITY_NAME" "1 Freq_div_2 " "Info: Found entity 1: Freq_div_2" {  } { { "Freq_div_2.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/Freq_div_2.v" 9 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Counter_N.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Counter_N.v" { { "Info" "ISGN_ENTITY_NAME" "1 Counter_N " "Info: Found entity 1: Counter_N" {  } { { "Counter_N.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/Counter_N.v" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "D:/Prac/QuartusII/Frequency_divider/Block1.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "F_Div_20.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file F_Div_20.v" { { "Info" "ISGN_ENTITY_NAME" "1 F_Div_20 " "Info: Found entity 1: F_Div_20" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "F_Div_20 " "Info: Elaborating entity \"F_Div_20\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 F_Div_20.v(12) " "Warning: Verilog HDL assignment warning at F_Div_20.v(12): truncated value with size 32 to match size of target (8)" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 F_Div_20.v(13) " "Warning: Verilog HDL assignment warning at F_Div_20.v(13): truncated value with size 32 to match size of target (1)" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 F_Div_20.v(19) " "Warning: Verilog HDL assignment warning at F_Div_20.v(19): truncated value with size 32 to match size of target (8)" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 19 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 F_Div_20.v(22) " "Warning: Verilog HDL assignment warning at F_Div_20.v(22): truncated value with size 32 to match size of target (8)" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 22 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "15 " "Info: Implemented 15 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "12 " "Info: Implemented 12 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 17 15:20:52 2008 " "Info: Processing ended: Sun Aug 17 15:20:52 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}