frequency_divider.fit.qmsg

用VERILOG HDL实现的任意 频率分频器源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Aug 17 15:20:53 2008 " "Info: Processing started: Sun Aug 17 15:20:53 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Frequency_divider -c Frequency_divider " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Frequency_divider -c Frequency_divider" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "Frequency_divider EP1C3T100C6 " "Info: Selected device EP1C3T100C6 for design \"Frequency_divider\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " {  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "3 3 " "Info: No exact pin location assignment(s) for 3 pins of 3 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Fout " "Info: Pin Fout not assigned to an exact location on the device" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 4 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Fout" } } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Fout } "NODE_NAME" } "" } } { "D:/Prac/QuartusII/Frequency_divider/Frequency_divider.fld" "" { Floorplan "D:/Prac/QuartusII/Frequency_divider/Frequency_divider.fld" "" "" { Fout } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Reset_N " "Info: Pin Reset_N not assigned to an exact location on the device" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Reset_N" } } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Reset_N } "NODE_NAME" } "" } } { "D:/Prac/QuartusII/Frequency_divider/Frequency_divider.fld" "" { Floorplan "D:/Prac/QuartusII/Frequency_divider/Frequency_divider.fld" "" "" { Reset_N } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "Fin " "Info: Pin Fin not assigned to an exact location on the device" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "Fin" } } } } { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { Fin } "NODE_NAME" } "" } } { "D:/Prac/QuartusII/Frequency_divider/Frequency_divider.fld" "" { Floorplan "D:/Prac/QuartusII/Frequency_divider/Frequency_divider.fld" "" "" { Fin } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "Fin Global clock in PIN 10 " "Info: Automatically promoted signal \"Fin\" to use Global clock in PIN 10" {  } { { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "2 unused 3.30 1 1 0 " "Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 1 input, 1 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 11 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  11 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 17 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 17 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 17 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  17 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.620 ns register register " "Info: Estimated most critical path is register to register delay of 2.620 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns j\[4\] 1 REG LAB_X2_Y2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X2_Y2; Fanout = 3; REG Node = 'j\[4\]'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "" { j[4] } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.288 ns) + CELL(0.454 ns) 0.742 ns reduce_nor~41 2 COMB LAB_X1_Y2 2 " "Info: 2: + IC(0.288 ns) + CELL(0.454 ns) = 0.742 ns; Loc. = LAB_X1_Y2; Fanout = 2; COMB Node = 'reduce_nor~41'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "0.742 ns" { j[4] reduce_nor~41 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.225 ns) 1.429 ns j\[6\]~213 3 COMB LAB_X2_Y2 8 " "Info: 3: + IC(0.462 ns) + CELL(0.225 ns) = 1.429 ns; Loc. = LAB_X2_Y2; Fanout = 8; COMB Node = 'j\[6\]~213'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "0.687 ns" { reduce_nor~41 j[6]~213 } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.335 ns) + CELL(0.856 ns) 2.620 ns j\[1\] 4 REG LAB_X2_Y2 4 " "Info: 4: + IC(0.335 ns) + CELL(0.856 ns) = 2.620 ns; Loc. = LAB_X2_Y2; Fanout = 4; REG Node = 'j\[1\]'" {  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "1.191 ns" { j[6]~213 j[1] } "NODE_NAME" } "" } } { "F_Div_20.v" "" { Text "D:/Prac/QuartusII/Frequency_divider/F_Div_20.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.535 ns 58.59 % " "Info: Total cell delay = 1.535 ns ( 58.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.085 ns 41.41 % " "Info: Total interconnect delay = 1.085 ns ( 41.41 % )" {  } {  } 0}  } { { "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" "" { Report "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider_cmp.qrpt" Compiler "Frequency_divider" "UNKNOWN" "V1" "D:/Prac/QuartusII/Frequency_divider/db/Frequency_divider.quartus_db" { Floorplan "D:/Prac/QuartusII/Frequency_divider/" "" "2.620 ns" { j[4] reduce_nor~41 j[6]~213 j[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Aug 17 15:20:55 2008 " "Info: Processing ended: Sun Aug 17 15:20:55 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}