freq_div_2.v

用VERILOG HDL实现的任意 频率分频器源代码

//--------------------------------------//
//module name: Freq_div_2---------------//
//file   name: Freq_div_2.v-------------//
//module function:
//            2 frequency divider-------//
//Coder      : h0nly--------------------//
//Time       : 2008-08-13th 11:00pm-----//
//--------------------------------------//
module Freq_div_2(clk_in, 
                  clk_out
                  );
//output ports----------------------------
output clk_out;
//input ports----------------------------
input  clk_in;
//
reg    clk_out;
//code starts here------------------------
always @ (posedge clk_in) begin
	clk_out = ~clk_out;
end
//
endmodule//End of Module Freq_div_2