frequency_divider.fit.eqn

用VERILOG HDL实现的任意 频率分频器源代码

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--A1L3Q is Fout~reg0 at LC_X1_Y2_N3
--operation mode is normal

A1L3Q_lut_out = Reset_N & (A1L3Q $ (!A1L03 & !A1L13));
A1L3Q = DFFEAS(A1L3Q_lut_out, GLOBAL(Fin), VCC, , , , , , );


--j[1] is j[1] at LC_X2_Y2_N1
--operation mode is arithmetic

j[1]_lut_out = j[1] $ (A1L7);
j[1] = DFFEAS(j[1]_lut_out, GLOBAL(Fin), VCC, , , , , A1L82, );

--A1L01 is j[1]~182 at LC_X2_Y2_N1
--operation mode is arithmetic

A1L01_cout_0 = !A1L7 # !j[1];
A1L01 = CARRY(A1L01_cout_0);

--A1L11 is j[1]~182COUT1_216 at LC_X2_Y2_N1
--operation mode is arithmetic

A1L11_cout_1 = !A1L8 # !j[1];
A1L11 = CARRY(A1L11_cout_1);


--j[2] is j[2] at LC_X2_Y2_N2
--operation mode is arithmetic

j[2]_lut_out = j[2] $ (!A1L01);
j[2] = DFFEAS(j[2]_lut_out, GLOBAL(Fin), VCC, , , , , A1L82, );

--A1L31 is j[2]~186 at LC_X2_Y2_N2
--operation mode is arithmetic

A1L31_cout_0 = j[2] & (!A1L01);
A1L31 = CARRY(A1L31_cout_0);

--A1L41 is j[2]~186COUT1_217 at LC_X2_Y2_N2
--operation mode is arithmetic

A1L41_cout_1 = j[2] & (!A1L11);
A1L41 = CARRY(A1L41_cout_1);


--j[0] is j[0] at LC_X2_Y2_N0
--operation mode is arithmetic

j[0]_lut_out = !j[0];
j[0] = DFFEAS(j[0]_lut_out, GLOBAL(Fin), VCC, , , , , A1L82, );

--A1L7 is j[0]~190 at LC_X2_Y2_N0
--operation mode is arithmetic

A1L7_cout_0 = j[0];
A1L7 = CARRY(A1L7_cout_0);

--A1L8 is j[0]~190COUT1_215 at LC_X2_Y2_N0
--operation mode is arithmetic

A1L8_cout_1 = j[0];
A1L8 = CARRY(A1L8_cout_1);


--j[3] is j[3] at LC_X2_Y2_N3
--operation mode is arithmetic

j[3]_lut_out = j[3] $ A1L31;
j[3] = DFFEAS(j[3]_lut_out, GLOBAL(Fin), VCC, , , , , A1L82, );

--A1L61 is j[3]~194 at LC_X2_Y2_N3
--operation mode is arithmetic

A1L61_cout_0 = !A1L31 # !j[3];
A1L61 = CARRY(A1L61_cout_0);

--A1L71 is j[3]~194COUT1 at LC_X2_Y2_N3
--operation mode is arithmetic

A1L71_cout_1 = !A1L41 # !j[3];
A1L71 = CARRY(A1L71_cout_1);


--A1L03 is reduce_nor~40 at LC_X2_Y2_N9
--operation mode is normal

A1L03 = j[1] # j[2] # !j[3] # !j[0];


--j[4] is j[4] at LC_X2_Y2_N4
--operation mode is arithmetic

j[4]_lut_out = j[4] $ !A1L61;
j[4] = DFFEAS(j[4]_lut_out, GLOBAL(Fin), VCC, , , , , A1L82, );

--A1L91 is j[4]~198 at LC_X2_Y2_N4
--operation mode is arithmetic

A1L91 = A1L02;


--j[5] is j[5] at LC_X2_Y2_N5
--operation mode is arithmetic

j[5]_carry_eqn = (!A1L91 & GND) # (A1L91 & VCC);
j[5]_lut_out = j[5] $ j[5]_carry_eqn;
j[5] = DFFEAS(j[5]_lut_out, GLOBAL(Fin), VCC, , , , , A1L82, );

--A1L32 is j[5]~202 at LC_X2_Y2_N5
--operation mode is arithmetic

A1L32_cout_0 = !A1L91 # !j[5];
A1L32 = CARRY(A1L32_cout_0);

--A1L42 is j[5]~202COUT1_218 at LC_X2_Y2_N5
--operation mode is arithmetic

A1L42_cout_1 = !A1L91 # !j[5];
A1L42 = CARRY(A1L42_cout_1);


--j[6] is j[6] at LC_X2_Y2_N6
--operation mode is arithmetic

j[6]_carry_eqn = (!A1L91 & A1L32) # (A1L91 & A1L42);
j[6]_lut_out = j[6] $ (!j[6]_carry_eqn);
j[6] = DFFEAS(j[6]_lut_out, GLOBAL(Fin), VCC, , , , , A1L82, );

--A1L62 is j[6]~206 at LC_X2_Y2_N6
--operation mode is arithmetic

A1L62_cout_0 = j[6] & (!A1L32);
A1L62 = CARRY(A1L62_cout_0);

--A1L72 is j[6]~206COUT1_219 at LC_X2_Y2_N6
--operation mode is arithmetic

A1L72_cout_1 = j[6] & (!A1L42);
A1L72 = CARRY(A1L72_cout_1);


--j[7] is j[7] at LC_X2_Y2_N7
--operation mode is normal

j[7]_carry_eqn = (!A1L91 & A1L62) # (A1L91 & A1L72);
j[7]_lut_out = j[7] $ (j[7]_carry_eqn);
j[7] = DFFEAS(j[7]_lut_out, GLOBAL(Fin), VCC, , , , , A1L82, );


--A1L13 is reduce_nor~41 at LC_X1_Y2_N2
--operation mode is normal

A1L13 = j[7] # j[4] # j[5] # j[6];


--A1L82 is j[6]~213 at LC_X2_Y2_N8
--operation mode is normal

A1L82 = !A1L13 & !A1L03 # !Reset_N;


--Reset_N is Reset_N at PIN_23
--operation mode is input

Reset_N = INPUT();


--Fin is Fin at PIN_10
--operation mode is input

Fin = INPUT();


--Fout is Fout at PIN_22
--operation mode is output

Fout = OUTPUT(A1L3Q);