frequency_divider.tan.rpt

用VERILOG HDL实现的任意 频率分频器源代码

+---------------+-------------+-----------+---------+-----------+----------+
; N/A           ; None        ; -3.093 ns ; Reset_N ; Fout~reg0 ; Fin      ;
; N/A           ; None        ; -4.119 ns ; Reset_N ; j[1]      ; Fin      ;
; N/A           ; None        ; -4.119 ns ; Reset_N ; j[0]      ; Fin      ;
; N/A           ; None        ; -4.119 ns ; Reset_N ; j[7]      ; Fin      ;
; N/A           ; None        ; -4.119 ns ; Reset_N ; j[4]      ; Fin      ;
; N/A           ; None        ; -4.119 ns ; Reset_N ; j[5]      ; Fin      ;
; N/A           ; None        ; -4.119 ns ; Reset_N ; j[6]      ; Fin      ;
; N/A           ; None        ; -4.119 ns ; Reset_N ; j[2]      ; Fin      ;
; N/A           ; None        ; -4.119 ns ; Reset_N ; j[3]      ; Fin      ;
+---------------+-------------+-----------+---------+-----------+----------+


+-----------------------------------------------------------------------------------------------------------+
; Ignored Timing Assignments                                                                                ;
+----------------+---------+------+--------+-------------+--------------------------------------------------+
; Option         ; Setting ; From ; To     ; Entity Name ; Help                                             ;
+----------------+---------+------+--------+-------------+--------------------------------------------------+
; Clock Settings ; clk in  ;      ; clk_in ;             ; No element named clk_in was found in the netlist ;
+----------------+---------+------+--------+-------------+--------------------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Aug 17 15:20:58 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Frequency_divider -c Frequency_divider --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "Fin" is an undefined clock
Warning: Clock Setting "clk_in" is unassigned
Info: Clock "Fin" has Internal fmax of 303.95 MHz between source register "j[7]" and destination register "j[3]" (period= 3.29 ns)
    Info: + Longest register to register delay is 3.088 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y2_N7; Fanout = 2; REG Node = 'j[7]'
        Info: 2: + IC(0.573 ns) + CELL(0.454 ns) = 1.027 ns; Loc. = LC_X1_Y2_N2; Fanout = 2; COMB Node = 'reduce_nor~41'
        Info: 3: + IC(0.511 ns) + CELL(0.340 ns) = 1.878 ns; Loc. = LC_X2_Y2_N8; Fanout = 8; COMB Node = 'j[6]~213'
        Info: 4: + IC(0.354 ns) + CELL(0.856 ns) = 3.088 ns; Loc. = LC_X2_Y2_N3; Fanout = 4; REG Node = 'j[3]'
        Info: Total cell delay = 1.650 ns ( 53.43 % )
        Info: Total interconnect delay = 1.438 ns ( 46.57 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "Fin" to destination register is 2.099 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'
            Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N3; Fanout = 4; REG Node = 'j[3]'
            Info: Total cell delay = 1.677 ns ( 79.90 % )
            Info: Total interconnect delay = 0.422 ns ( 20.10 % )
        Info: - Longest clock path from clock "Fin" to source register is 2.099 ns
            Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'
            Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N7; Fanout = 2; REG Node = 'j[7]'
            Info: Total cell delay = 1.677 ns ( 79.90 % )
            Info: Total interconnect delay = 0.422 ns ( 20.10 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Micro setup delay of destination is 0.029 ns
Info: tsu for register "j[1]" (data pin = "Reset_N", clock pin = "Fin") is 4.160 ns
    Info: + Longest pin to register delay is 6.230 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 2; PIN Node = 'Reset_N'
        Info: 2: + IC(3.802 ns) + CELL(0.088 ns) = 5.020 ns; Loc. = LC_X2_Y2_N8; Fanout = 8; COMB Node = 'j[6]~213'
        Info: 3: + IC(0.354 ns) + CELL(0.856 ns) = 6.230 ns; Loc. = LC_X2_Y2_N1; Fanout = 4; REG Node = 'j[1]'
        Info: Total cell delay = 2.074 ns ( 33.29 % )
        Info: Total interconnect delay = 4.156 ns ( 66.71 % )
    Info: + Micro setup delay of destination is 0.029 ns
    Info: - Shortest clock path from clock "Fin" to destination register is 2.099 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'
        Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X2_Y2_N1; Fanout = 4; REG Node = 'j[1]'
        Info: Total cell delay = 1.677 ns ( 79.90 % )
        Info: Total interconnect delay = 0.422 ns ( 20.10 % )
Info: tco from clock "Fin" to destination pin "Fout" through register "Fout~reg0" is 4.782 ns
    Info: + Longest clock path from clock "Fin" to source register is 2.099 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'
        Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X1_Y2_N3; Fanout = 2; REG Node = 'Fout~reg0'
        Info: Total cell delay = 1.677 ns ( 79.90 % )
        Info: Total interconnect delay = 0.422 ns ( 20.10 % )
    Info: + Micro clock to output delay of source is 0.173 ns
    Info: + Longest register to pin delay is 2.510 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y2_N3; Fanout = 2; REG Node = 'Fout~reg0'
        Info: 2: + IC(0.876 ns) + CELL(1.634 ns) = 2.510 ns; Loc. = PIN_22; Fanout = 0; PIN Node = 'Fout'
        Info: Total cell delay = 1.634 ns ( 65.10 % )
        Info: Total interconnect delay = 0.876 ns ( 34.90 % )
Info: th for register "Fout~reg0" (data pin = "Reset_N", clock pin = "Fin") is -3.093 ns
    Info: + Longest clock path from clock "Fin" to destination register is 2.099 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 9; CLK Node = 'Fin'
        Info: 2: + IC(0.422 ns) + CELL(0.547 ns) = 2.099 ns; Loc. = LC_X1_Y2_N3; Fanout = 2; REG Node = 'Fout~reg0'
        Info: Total cell delay = 1.677 ns ( 79.90 % )
        Info: Total interconnect delay = 0.422 ns ( 20.10 % )
    Info: + Micro hold delay of destination is 0.012 ns
    Info: - Shortest pin to register delay is 5.204 ns
        Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_23; Fanout = 2; PIN Node = 'Reset_N'
        Info: 2: + IC(3.506 ns) + CELL(0.568 ns) = 5.204 ns; Loc. = LC_X1_Y2_N3; Fanout = 2; REG Node = 'Fout~reg0'
        Info: Total cell delay = 1.698 ns ( 32.63 % )
        Info: Total interconnect delay = 3.506 ns ( 67.37 % )
Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Sun Aug 17 15:20:58 2008
    Info: Elapsed time: 00:00:01