frequency_divider.map.rpt

用VERILOG HDL实现的任意 频率分频器源代码

+------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                       ;
+----------------------------------+-----------------+------------------------+------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                   ;
+----------------------------------+-----------------+------------------------+------------------------------------------------+
; F_Div_20.v                       ; yes             ; User Verilog HDL File  ; D:/Prac/QuartusII/Frequency_divider/F_Div_20.v ;
+----------------------------------+-----------------+------------------------+------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 12      ;
; Total combinational functions     ; 12      ;
;     -- Total 4-input functions    ; 3       ;
;     -- Total 3-input functions    ; 1       ;
;     -- Total 2-input functions    ; 0       ;
;     -- Total 1-input functions    ; 8       ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 9       ;
; Total logic cells in carry chains ; 8       ;
; I/O pins                          ; 3       ;
; Maximum fan-out node              ; Fin     ;
; Maximum fan-out                   ; 9       ;
; Total fan-out                     ; 48      ;
; Average fan-out                   ; 3.20    ;
+-----------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |F_Div_20                  ; 12 (12)     ; 9            ; 0           ; 3    ; 0            ; 3 (3)        ; 0 (0)             ; 9 (9)            ; 8 (8)           ; |F_Div_20           ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 9     ;
; Number of registers using Synchronous Clear  ; 8     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |F_Div_20|j[6]             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/Prac/QuartusII/Frequency_divider/Frequency_divider.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sun Aug 17 15:20:52 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Frequency_divider -c Frequency_divider
Info: Found 1 design units, including 1 entities, in source file Frequency_divider.v
    Info: Found entity 1: Frequency_divider
Info: Found 1 design units, including 1 entities, in source file Half_sel.v
    Info: Found entity 1: Half_sel
Info: Found 1 design units, including 1 entities, in source file Freq_div_2.v
    Info: Found entity 1: Freq_div_2
Info: Found 1 design units, including 1 entities, in source file Counter_N.v
    Info: Found entity 1: Counter_N
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
    Info: Found entity 1: Block1
Info: Found 1 design units, including 1 entities, in source file F_Div_20.v
    Info: Found entity 1: F_Div_20
Info: Elaborating entity "F_Div_20" for the top level hierarchy
Warning: Verilog HDL assignment warning at F_Div_20.v(12): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at F_Div_20.v(13): truncated value with size 32 to match size of target (1)
Warning: Verilog HDL assignment warning at F_Div_20.v(19): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at F_Div_20.v(22): truncated value with size 32 to match size of target (8)
Info: Implemented 15 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 12 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Sun Aug 17 15:20:52 2008
    Info: Elapsed time: 00:00:01