frequency_divider.map.summary

用VERILOG HDL实现的任意 频率分频器源代码

Flow Status : Successful - Sun Aug 17 15:20:52 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : Frequency_divider
Top-level Entity Name : F_Div_20
Family : Cyclone
Device : EP1C3T100C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 12
Total pins : 3
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0