frequency_divider.fit.summary

来自「用VERILOG HDL实现的任意 频率分频器源代码」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Sun Aug 17 15:20:55 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : Frequency_divider
Top-level Entity Name : F_Div_20
Family : Cyclone
Device : EP1C3T100C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 12 / 2,910 ( < 1 % )
Total pins : 3 / 65 ( 4 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )