frequency_divider.tan.summary

来自「用VERILOG HDL实现的任意 频率分频器源代码」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.160 ns
From           : Reset_N
To             : j[3]
From Clock     : 
To Clock       : Fin
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 4.782 ns
From           : Fout~reg0
To             : Fout
From Clock     : Fin
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.093 ns
From           : Reset_N
To             : Fout~reg0
From Clock     : 
To Clock       : Fin
Failed Paths   : 0

Type           : Clock Setup: 'Fin'
Slack          : N/A
Required Time  : None
Actual Time    : 303.95 MHz ( period = 3.290 ns )
From           : j[7]
To             : j[1]
From Clock     : Fin
To Clock       : Fin
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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