counter_n.v

用VERILOG HDL实现的任意 频率分频器源代码

//--------------------------------------//
//module name: Counter_N----------------//
//file   name: Counter_N.v--------------//
//module function:
//            counter with the mod of N-//
//            7 freq_div & 6.5 fre_div--//
//Coder      : h0nly--------------------//
//Time       : 2008-08-13th 11:00pm-----//
//--------------------------------------//
module Counter_N(reset,
				 en,
				 clk_in,
				 //-------
				 clk_out,
				 count
				 );
//
parameter N = 7;
//output ports----------------------------
output [7:0] count;
output       clk_out;
//input ports----------------------------
input        reset;
input        en;
input        clk_in;
//
reg          clk_out;
reg    [7:0] count;
//code starts here------------------------

//count+1---------------------------------
always @ (posedge clk_in) begin
	if(reset) begin
		count = 8'd0;  //count[7:0] clear 
	end//end of if
	//
	else if(en) begin 
		if(count==(N-1)) count = 8'd0;
		else             count = count +8'd1;
	end//end of else if
end//end of always------------------------

always  begin
	if     (N<=2)   clk_out = count[0];
	else if(N<=4)	clk_out = count[1];
	else if(N<=8)	clk_out = count[2];
	else if(N<=16)	clk_out = count[3];
	else if(N<=32)	clk_out = count[4];
	else if(N<=64)	clk_out = count[5];
	else if(N<=128)	clk_out = count[6];
	else if(N<=256)	clk_out = count[7];
end//end of always
//
endmodule//end of module Counter_N