frequency_divider.qsf

用VERILOG HDL实现的任意 频率分频器源代码

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		Frequency_divider_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:24:08  AUGUST 15, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VERILOG_FILE Frequency_divider.v
set_global_assignment -name VERILOG_FILE Half_sel.v
set_global_assignment -name VERILOG_FILE Freq_div_2.v
set_global_assignment -name VERILOG_FILE Counter_N.v
set_global_assignment -name BDF_FILE Block1.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Frequency_divider.vwf
set_global_assignment -name VERILOG_FILE F_Div_20.v

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY F_Div_20

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C3T100C6
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# -------------------
# start CLOCK(clk_in)

	# Timing Assignments
	# ==================
	set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id clk_in

# end CLOCK(clk_in)
# -----------------

# ----------------------
# start ENTITY(F_Div_20)

	# Timing Assignments
	# ==================
	set_instance_assignment -name CLOCK_SETTINGS clk_in -to clk_in

# end ENTITY(F_Div_20)
# --------------------