half_sel.v

用VERILOG HDL实现的任意 频率分频器源代码

//--------------------------------------//
//module name: Half_sel-----------------//
//file   name: Half_sel.v---------------//
//module function:
//            Xor select module---------//
//Coder      : h0nly--------------------//
//Time       : 2008-08-13th 11:00pm-----//
//--------------------------------------//
module Half_sel(sel,
				a,
				b,
				c
				);
//output ports----------------------------
output c;
//input  ports----------------------------
input  b, a;
input  sel;
//inner parameter declaration-------------
wire   w;
//code starts here------------------------
xor xor_ (w, a, b);
//----------------------------------------
//sel |  function
//----------------------------------------
// 1  |  half_integer_Freq_div
// 0  |  integer_Freq_div
//----------------------------------------
assign c = sel ? w : a;
//
endmodule//End Of Module Half_sel