alu_4.v

用verilog语言编写的4位算术逻辑单元ALU,功能参考74181

module alu_4(F,c_out,a,b,s,c_in,m);
output [3:0] F;
output c_out;
input [3:0] a,b,s;
input c_in,m;

wire [3:0] f,p,g,c;
alu_1 alu0(f[0],p[0],g[0],s,a[0],b[0]);
alu_1 alu1(f[1],p[1],g[1],s,a[1],b[1]);
alu_1 alu2(f[2],p[2],g[2],s,a[2],b[2]);
alu_1 alu3(f[3],p[3],g[3],s,a[3],b[3]);

assign /*c[0]=(c_in&p[0])|g[0],
       c[1]=(c[0]&p[1])|g[1],
       c[2]=(c[1]&p[2])|g[2],
       c[3]=(c[2]&p[3])|g[3],*/
       c[0]=(c_in&p[0])|g[0],
	   c[1]=(c_in&p[0]&p[1])|(g[0]&p[1])|g[1],
	   c[2]=(c_in&p[0]&p[1]&p[2])|(g[0]&p[1]&p[2])|(g[1]&p[2])|g[2],
	   c[3]=(c_in&p[0]&p[1]&p[2]&p[3])|(g[0]&p[1]&p[2]&p[3])|(g[1]&p[2]&p[3])|(g[2]&p[3])|g[3],
	   F[0]=f[0]^(~m&c_in),
	   F[1]=f[1]^(~m&c[0]),
	   F[2]=f[2]^(~m&c[1]),
	   F[3]=f[3]^(~m&c[2]);	
	
assign c_out=c[3];
endmodule 

module alu_1(f,p,g,s,a,b);
output f,p,g;
input [3:0] s;
input a,b;
assign p=(~(s[2]&a&~b))&(~(s[3]&a&b)),
       g=~((s[0]|a|~b)&(s[1]|a|b));
       
assign f=~(~g&p);
endmodule