dds.tan.rpt

实现dds功能

Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Type                                                    ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                      ; To                                                                                                                                        ; From Clock                               ; To Clock                                 ; Failed Paths ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+
; Worst-case tsu                                          ; N/A       ; None                             ; 5.205 ns                         ; ps2_clk                                                                                                                                   ; pword:inst11|dat[4]                                                                                                                       ; --                                       ; clk                                      ; 0            ;
; Worst-case tco                                          ; N/A       ; None                             ; 14.313 ns                        ; fword:inst9|code[3]                                                                                                                       ; code[3]                                                                                                                                   ; clk                                      ; --                                       ; 0            ;
; Worst-case tpd                                          ; N/A       ; None                             ; 7.535 ns                         ; dip                                                                                                                                       ; altera_auto_signaltap_0_dip_ae                                                                                                            ; --                                       ; --                                       ; 0            ;
; Worst-case th                                           ; N/A       ; None                             ; 3.714 ns                         ; altera_internal_jtag~TDIUTAP                                                                                                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|lpm_shiftreg:status_register|dffs[16]                                ; --                                       ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Setup: 'clk'                                      ; -3.849 ns ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_address_reg7 ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1]                                                ; pllu:inst3|altpll:altpll_component|_clk0 ; clk                                      ; 256          ;
; Clock Setup: 'pllu:inst3|altpll:altpll_component|_clk0' ; 44.923 ns ; 20.00 MHz ( period = 49.999 ns ) ; 197.01 MHz ( period = 5.076 ns ) ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7 ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'             ; N/A       ; None                             ; 47.00 MHz ( period = 21.276 ns ) ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[2]                                                                                               ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                          ; altera_internal_jtag~TCKUTAP             ; altera_internal_jtag~TCKUTAP             ; 0            ;
; Clock Hold: 'clk'                                       ; 0.822 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]           ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]           ; clk                                      ; clk                                      ; 0            ;
; Clock Hold: 'pllu:inst3|altpll:altpll_component|_clk0'  ; 1.065 ns  ; 20.00 MHz ( period = 49.999 ns ) ; N/A                              ; reg32b:inst1|dout[31]                                                                                                                     ; reg32b:inst1|dout[31]                                                                                                                     ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                            ;           ;                                  ;                                  ;                                                                                                                                           ;                                                                                                                                           ;                                          ;                                          ; 256          ;
+---------------------------------------------------------+-----------+----------------------------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;