dds.tan.rpt

来自「实现dds功能」· RPT 代码 · 共 194 行 · 第 1/5 页

; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                           ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                          ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pllu:inst3|altpll:altpll_component|_clk0 ;                    ; PLL output ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clk      ; 5                     ; 12                  ; -1.885 ns ;              ;
; clk                                      ;                    ; User Pin   ; 48.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP             ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pllu:inst3|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                      ; To                                                                                                                                         ; From Clock                               ; To Clock                                 ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------+------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7  ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg6 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg6  ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg5 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg5  ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg4 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg4  ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg3 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg3  ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg2 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg2  ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg1 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg1  ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg0 ; date_rom:inst10|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg0  ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg7  ; date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg7   ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg6  ; date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg6   ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;
; 44.923 ns                               ; 197.01 MHz ( period = 5.076 ns )                    ; date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_datain_reg5  ; date_rom:inst2|altsyncram:altsyncram_component|altsyncram_tr51:auto_generated|altsyncram_aa72:altsyncram1|ram_block3a7~porta_memory_reg5   ; pllu:inst3|altpll:altpll_component|_clk0 ; pllu:inst3|altpll:altpll_component|_clk0 ; 49.999 ns                   ; 49.242 ns                 ; 4.319 ns                ;