crc_d8.txt

Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8

///////////////////////////////////////////////////////////////////////
// File:  CRC8_D8.v                             
// Date:  Tue Aug 12 04:56:31 2008                                                      
//                                                                     
// Copyright (C) 1999-2003 Easics NV.                 
// This source file may be used and distributed without restriction    
// provided that this copyright statement is not removed from the file 
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
//   * polynomial: (0 1 8)
//   * data width: 8
//                                                                     
//                            
///////////////////////////////////////////////////////////////////////


module CRC8_D8;

  // polynomial: (0 1 8)
  // data width: 8
  // convention: the first serial data bit is D[7]
  function [7:0] nextCRC8_D8;

    input [7:0] Data;
    input [7:0] CRC;

    reg [7:0] D;
    reg [7:0] C;
    reg [7:0] NewCRC;

  begin

    D = Data;
    C = CRC;

    NewCRC[0] = D[7] ^ D[0] ^ C[0] ^ C[7];
    NewCRC[1] = D[7] ^ D[1] ^ D[0] ^ C[0] ^ C[1] ^ C[7];
    NewCRC[2] = D[2] ^ D[1] ^ C[1] ^ C[2];
    NewCRC[3] = D[3] ^ D[2] ^ C[2] ^ C[3];
    NewCRC[4] = D[4] ^ D[3] ^ C[3] ^ C[4];
    NewCRC[5] = D[5] ^ D[4] ^ C[4] ^ C[5];
    NewCRC[6] = D[6] ^ D[5] ^ C[5] ^ C[6];
    NewCRC[7] = D[7] ^ D[6] ^ C[6] ^ C[7];

    nextCRC8_D8 = NewCRC;

  end

  endfunction

endmodule