_primary.vhd

电机控制的程序例程

library verilog;
use verilog.vl_types.all;
entity clk_gen is
    port(
        div_by_2        : out    vl_logic;
        div_by_32       : out    vl_logic;
        div_by_64       : out    vl_logic;
        div_by_128      : out    vl_logic;
        div_by_256      : out    vl_logic;
        div_by_512      : out    vl_logic;
        div_by_1k       : out    vl_logic;
        div_by_2k       : out    vl_logic;
        div_by_4k       : out    vl_logic;
        div_by_16k      : out    vl_logic;
        div_by_32k      : out    vl_logic;
        div_by_64k      : out    vl_logic;
        div_by_128k     : out    vl_logic;
        div_by_256k     : out    vl_logic;
        div_by_512k     : out    vl_logic;
        div_by_1024k    : out    vl_logic;
        clk_10mhz       : in     vl_logic;
        rst_l           : in     vl_logic
    );
end clk_gen;