top_modelsim.xrf

ddr2 controller功能控制,里面有四个模块

instance = net, zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a7_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|data_out_reg[7]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a6_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|data_out_reg[6]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a5_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|data_out_reg[5]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a4_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|data_out_reg[4]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a3_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|data_out_reg[3]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a2_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|data_out_reg[2]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a1_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|data_out_reg[1]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a0_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|data_out_reg[0]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a16_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[16]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a16_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[16]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a15_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[15]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a15_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[15]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a14_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[14]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a14_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[14]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a13_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[13]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a13_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[13]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a12_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[12]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a12_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[12]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a11_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[11]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a11_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[11]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a10_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[10]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a10_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[10]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a9_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[9]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a9_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[9]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a8_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[8]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a8_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[8]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a7_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[7]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a7_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[7]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a6_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[6]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a6_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[6]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a5_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[5]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a5_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[5]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a4_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[4]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a4_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[4]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a3_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[3]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a3_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[3]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a2_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[2]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a2_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[2]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a1_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[1]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a1_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[1]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a0_a_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_reg[0]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a0_a_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_addr[0]~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_rw_n_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_rw_n~reg0, top, 1
instance = net, ADDR_ADV_LD_N_acombout, ADDR_ADV_LD_N, top, 1
instance = net, zbt_ctrl_top_inst1_apipe_stage1_aaddr_adv_ld_n_reg_areg0, zbt_ctrl_top_inst1|pipe_stage1|addr_adv_ld_n_reg~reg0, top, 1
instance = net, zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_adv_ld_n_areg0, zbt_ctrl_top_inst1|addr_ctrl_out1|ram_adv_ld_n~reg0, top, 1
instance = comp, DQ_a34_a_aI, DQ[34], top, 1
instance = comp, DQ_a28_a_aI, DQ[28], top, 1
instance = comp, DQ_a23_a_aI, DQ[23], top, 1
instance = comp, DQ_a22_a_aI, DQ[22], top, 1
instance = comp, DQ_a0_a_aI, DQ[0], top, 1
instance = comp, DQ_a26_a_aI, DQ[26], top, 1
instance = comp, DQ_a31_a_aI, DQ[31], top, 1
instance = comp, DQ_a14_a_aI, DQ[14], top, 1
instance = comp, DQ_a16_a_aI, DQ[16], top, 1
instance = comp, DQ_a11_a_aI, DQ[11], top, 1
instance = comp, DQ_a9_a_aI, DQ[9], top, 1
instance = comp, DQ_a35_a_aI, DQ[35], top, 1
instance = comp, DQ_a10_a_aI, DQ[10], top, 1
instance = comp, DQ_a21_a_aI, DQ[21], top, 1
instance = comp, DQ_a6_a_aI, DQ[6], top, 1
instance = comp, DQ_a3_a_aI, DQ[3], top, 1
instance = comp, DQ_a33_a_aI, DQ[33], top, 1
instance = comp, DQ_a30_a_aI, DQ[30], top, 1
instance = comp, DQ_a24_a_aI, DQ[24], top, 1
instance = comp, DQ_a2_a_aI, DQ[2], top, 1
instance = comp, DQ_a1_a_aI, DQ[1], top, 1
instance = comp, DQ_a27_a_aI, DQ[27], top, 1
instance = comp, DQ_a25_a_aI, DQ[25], top, 1
instance = comp, DQ_a32_a_aI, DQ[32], top, 1
instance = comp, DQ_a18_a_aI, DQ[18], top, 1
instance = comp, DQ_a15_a_aI, DQ[15], top, 1
instance = comp, DQ_a29_a_aI, DQ[29], top, 1
instance = comp, DQ_a12_a_aI, DQ[12], top, 1
instance = comp, DQ_a8_a_aI, DQ[8], top, 1
instance = comp, DQ_a20_a_aI, DQ[20], top, 1
instance = comp, DQ_a7_a_aI, DQ[7], top, 1
instance = comp, DQ_a17_a_aI, DQ[17], top, 1
instance = comp, DQ_a13_a_aI, DQ[13], top, 1
instance = comp, DQ_a5_a_aI, DQ[5], top, 1
instance = comp, DQ_a4_a_aI, DQ[4], top, 1
instance = comp, DQ_a19_a_aI, DQ[19], top, 1
instance = comp, clk_aI, clk, top, 1
instance = comp, PLL1_inst_aaltpll_component_apll, PLL1_inst|altpll_component|pll, top, 1
instance = comp, DM_a2_a_aI, DM[2], top, 1
instance = comp, RESET_N_aI, RESET_N, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a2_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|dm_reg[2]~reg0, top, 1
instance = comp, DM_a0_a_aI, DM[0], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a0_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|dm_reg[0]~reg0, top, 1
instance = comp, DM_a3_a_aI, DM[3], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a3_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|dm_reg[3]~reg0, top, 1
instance = comp, DM_a1_a_aI, DM[1], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a1_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|dm_reg[1]~reg0, top, 1
instance = comp, DATA_IN_a34_a_aI, DATA_IN[34], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a34_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[34]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a34_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][34], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a34_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[1][34], top, 1
instance = comp, RD_WR_N_aI, RD_WR_N, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_ard_wr_n_reg_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|rd_wr_n_reg~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a0_a_aI, zbt_ctrl_top_inst1|pipe_delay1|rw_n_pipe[0], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a_aI, zbt_ctrl_top_inst1|pipe_delay1|rw_n_pipe[1], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a_aI, zbt_ctrl_top_inst1|pipe_delay1|rw_n_pipe[2], top, 1
instance = comp, DATA_IN_a28_a_aI, DATA_IN[28], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a28_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[28]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a28_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][28], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a28_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[1][28], top, 1
instance = comp, DATA_IN_a23_a_aI, DATA_IN[23], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a23_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[23]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a23_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][23], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a23_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[1][23], top, 1
instance = comp, DATA_IN_a22_a_aI, DATA_IN[22], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a22_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[22]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a22_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][22], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a22_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[1][22], top, 1
instance = comp, DATA_IN_a0_a_aI, DATA_IN[0], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a0_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[0]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a0_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][0], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a0_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[1][0], top, 1
instance = comp, DATA_IN_a26_a_aI, DATA_IN[26], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a26_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[26]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a26_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][26], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a26_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[1][26], top, 1
instance = comp, DATA_IN_a31_a_aI, DATA_IN[31], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a31_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[31]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a31_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][31], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a31_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[1][31], top, 1
instance = comp, DATA_IN_a14_a_aI, DATA_IN[14], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a14_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[14]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a14_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][14], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a14_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[1][14], top, 1
instance = comp, DATA_IN_a16_a_aI, DATA_IN[16], top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a16_a_areg0_I, zbt_ctrl_top_inst1|pipe_stage1|data_in_reg[16]~reg0, top, 1
instance = comp, zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a16_a_aI, zbt_ctrl_top_inst1|pipe_delay1|data_in_pipe[0][16], top, 1