top.vho

ddr2 controller功能控制,里面有四个模块

	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a18_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(18),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a18_a_areg0);

DQ_a15_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a15_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(15),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a15_a_areg0);

DQ_a29_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a29_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(29),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a29_a_areg0);

DQ_a12_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a12_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(12),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a12_a_areg0);

DQ_a8_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a8_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(8),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a8_a_areg0);

DQ_a20_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a20_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(20),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a20_a_areg0);

DQ_a7_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a7_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(7),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a7_a_areg0);

DQ_a17_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a17_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(17),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a17_a_areg0);

DQ_a13_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a13_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(13),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a13_a_areg0);

DQ_a5_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a5_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(5),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a5_a_areg0);

DQ_a4_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a4_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	ou